From patchwork Wed May 17 21:28:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 13245729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0FB8C77B7A for ; Wed, 17 May 2023 21:28:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ztVf/KBOse4M2eHqjgYv8fWQ1RfYfsNVHcMSTBhlBoU=; b=l7c/53Sm2lBVjk npZphzb3ugVJuFCN4OSz9OZn1diwgNRZU0g7Jj61dwSN5tEjWcyckUq7gJj3iUTiou4RAxGYzQlxI Wb2YVC8lJGurEstI2g/wE7ry6+rXXKdcox48ITi3PO5mfhjSAH0m73KPX6BOwTLV9ZIJ8nO5uojqB cANpp/gcKCnYL1VdqytFkzMi7FUSY7RUKac2OTsQKBbHIIZ0b9aiSv87IeVANN7knP/Wu79hgsVCk Rt7sy3im4WIj1U60QEhDbK4AdjrA7yrfEZSdJZI7EBOWx7c+4/ZwqRcOmNGH0pQRjTFISWg1Gw4lA agkGQk9QdnmpyuvXZ4bA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pzOh9-00B6tV-1I; Wed, 17 May 2023 21:28:27 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzOh2-00B6qd-1y for linux-arm-kernel@lists.infradead.org; Wed, 17 May 2023 21:28:22 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 31F5161CF2; Wed, 17 May 2023 21:28:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 36DFDC4339B; Wed, 17 May 2023 21:28:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684358899; bh=LNlFRojyikhWH1jqlxhpNbRqpf/+L7GdVH+Dvh7OxKo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l/SqSIGKvtQV7dTxdFZuD/uj/dTA96X4CggrzyfMb+zMu/EfENa5JlJ0uS4XJmEtr wi59VWD5fH46BKPe55ipdMAex6uO+jpYTOXD5Tc8vpWEMfIVgVySNAsXm3Z3Sv1MB8 1Wg52OHQ7Xly/5IsoGCH4s/l+3imX6E4HXR4tvM4/G9g3SYp78N0SgyIBsGt6D31Zc BJDOBU7/R8+ERLrreynQc0k2eYMuR6I1CeX7yodrC3qUwQGBmIDX1vb6sEvapXrcCD Nuf1kuXvSiXvdSoTtxtZiLr1atumVIs9IbQZXVUg9qD6E80sW6UohxRJ5Dxf33y1Fn 7vFWzJDEPFH2A== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: Ard Biesheuvel , Linus Walleij , Arnd Bergmann , Russell King , Nicolas Pitre Subject: [PATCH v2 2/8] ARM: vfp: Remove workaround for Feroceon CPUs Date: Wed, 17 May 2023 23:28:02 +0200 Message-Id: <20230517212808.3895190-3-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230517212808.3895190-1-ardb@kernel.org> References: <20230517212808.3895190-1-ardb@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3864; i=ardb@kernel.org; h=from:subject; bh=LNlFRojyikhWH1jqlxhpNbRqpf/+L7GdVH+Dvh7OxKo=; b=owGbwMvMwCFmkMcZplerG8N4Wi2JISXV7UH/F3WVYscje098vPdeIF3x2dWDClrcq+e+uZuXb FYZfPlnRykLgxgHg6yYIovA7L/vdp6eKFXrPEsWZg4rE8gQBi5OAZiIgiPDP+WC17F8p0881kx/ K1S9vL+r6lHLs6CeNA87tlna885cWMXIcEXIomv9YWGGedktgTeTc/hfBmcLLb6YK3BJ8cr7rgg 5NgA= X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230517_142820_736295_139C23C7 X-CRM114-Status: GOOD ( 21.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Feroceon CPUs have a non-standard implementation of VFP which reports synchronous VFP exceptions using the async VFP flag. This requires a workaround which is difficult to reconcile with other implementations, making it tricky to support both versions in a single image. Since this is a v5 CPU, it is not supported by armhf and so the likelihood that anybody is using this with recent distros/kernels and rely on the VFP at the same time is extremely low. So let's just disable VFP support on these cores, so we can remove the workaround. This will help future development to support v5 and v6 CPUs with a single kernel image. Reviewed-by: Linus Walleij Acked-by: Nicolas Pitre Acked-by: Arnd Bergmann Signed-off-by: Ard Biesheuvel --- arch/arm/mm/proc-feroceon.S | 4 ++++ arch/arm/vfp/vfphw.S | 4 ---- arch/arm/vfp/vfpmodule.c | 8 +++++--- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 61ce82aca6f0d603..072ff9b451f846bf 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -56,6 +56,10 @@ ENTRY(cpu_feroceon_proc_init) movne r2, r2, lsr #2 @ turned into # of sets sub r2, r2, #(1 << 5) stmia r1, {r2, r3} +#ifdef CONFIG_VFP + mov r1, #1 @ disable quirky VFP + str_l r1, VFP_arch_feroceon, r2 +#endif ret lr /* diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index a4610d0f321527cc..0aeb60ac3b5376a8 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -110,7 +110,6 @@ ENTRY(vfp_support_entry) beq vfp_reload_hw @ then the hw state needs reloading VFPFSTMIA r4, r5 @ save the working registers VFPFMRX r5, FPSCR @ current status -#ifndef CONFIG_CPU_FEROCEON tst r1, #FPEXC_EX @ is there additional state to save? beq 1f VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) @@ -118,7 +117,6 @@ ENTRY(vfp_support_entry) beq 1f VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) 1: -#endif stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 vfp_reload_hw: @@ -153,7 +151,6 @@ vfp_reload_hw: VFPFLDMIA r10, r5 @ reload the working registers while @ FPEXC is in a safe state ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 -#ifndef CONFIG_CPU_FEROCEON tst r1, #FPEXC_EX @ is there additional state to restore? beq 1f VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set) @@ -161,7 +158,6 @@ vfp_reload_hw: beq 1f VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present) 1: -#endif VFPFMXR FPSCR, r5 @ restore status @ The context stored in the VFP hardware is up to date with this thread diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 08d5dfcf70796eea..95628e57807b1e79 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -42,7 +42,11 @@ static bool have_vfp __ro_after_init; * Used in startup: set to non-zero if VFP checks fail * After startup, holds VFP architecture */ -static unsigned int __initdata VFP_arch; +static unsigned int VFP_arch; + +#ifdef CONFIG_CPU_FEROCEON +extern unsigned int VFP_arch_feroceon __alias(VFP_arch); +#endif /* * The pointer to the vfpstate structure of the thread which currently @@ -357,14 +361,12 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs) } if (fpexc & FPEXC_EX) { -#ifndef CONFIG_CPU_FEROCEON /* * Asynchronous exception. The instruction is read from FPINST * and the interrupted instruction has to be restarted. */ trigger = fmrx(FPINST); regs->ARM_pc -= 4; -#endif } else if (!(fpexc & FPEXC_DEX)) { /* * Illegal combination of bits. It can be caused by an