From patchwork Thu May 25 12:56:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13255217 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F556C7EE31 for ; Thu, 25 May 2023 12:57:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zUNJ1wk44vAB+qfvjU1bD73MwwXVaOQpZKGpVS0Xcwg=; b=MRgOkeAQvvL326 y79ClXwxiCYXrj7xB8YN6kfRG/UAkxrhPPTSTcy8CySTGF1zNzniIwkke2pKkoteYZ/sv/ZtfEHIH ARi3brRGw1t3sbmuJwrmsvEUDd79r/hmoOGcWMypCLHBzdzHV5Tz4hdN6kfKz/EFTqK5cG4+U6bbH W4CSvKsdYwpXigEqipU2Msb5xyF1Qxyuj17EDjQUF9E07m/BCNQ9xiPB2B5hRVdN5Lec1rFNlBaII hsV51Ok2mOHecjXK3lsJdidD/sx16dGQBz8RkXzOgSGukFbAXwEqzpT2pA7iFq8l5rfZRUrpYlQQF S073xZoq7hg6RN2ydMMw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q2AWy-00GffF-1t; Thu, 25 May 2023 12:57:24 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q2AWm-00GfYc-30 for linux-arm-kernel@lists.infradead.org; Thu, 25 May 2023 12:57:14 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685019432; x=1716555432; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EVnSI9LJi2wDVScFuluBr8cQysoQrwP3wKw1ykii7jI=; b=LXgbeZRpZqZxpnY0UjHY3tWwaGO0haU8/sWKmq4A1dhWp+fU6h1EfYy2 j92nPTjY57/A1/dt+fUO8nbQCnBBC79Fnj3FZhQWXeiiPOuEcXbbsj5KC fS3jqFLc5GGC6lTzBSEmOw2Xgf+C42K7bmN3TT5DrjWphyG4Osp/X2eUn 2GATC6RmfYPa/MwaNXb5pVYo2w1V0/XTvQl8uuunGlbrliDNzjFBHgzcC rFuPHKCGw/CY209wIo3QyZLwPzFtUFmSYGElB+weKmVXm0nzMwZtdKSSA 5epkaTXCiHlEnhKpgtNZticeyYadCPqJFSiBC4V6NjJiaX+j3HBtb9Wr5 Q==; X-IronPort-AV: E=Sophos;i="6.00,191,1681196400"; d="scan'208";a="214859631" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 May 2023 05:57:12 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 25 May 2023 05:57:11 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 25 May 2023 05:57:07 -0700 From: Claudiu Beznea To: , , , , , , , , , CC: , , , , "Claudiu Beznea" Subject: [PATCH 3/5] dt-bindings: timer: microchip,sam9x60-pit64b: convert to yaml Date: Thu, 25 May 2023 15:56:00 +0300 Message-ID: <20230525125602.640855-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525125602.640855-1-claudiu.beznea@microchip.com> References: <20230525125602.640855-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230525_055713_026920_82BE68B5 X-CRM114-Status: GOOD ( 15.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert Microchip PIT64B to YAML. Along with it clock-names binding has been added as the driver needs it to get PIT64B clocks. Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/arm/atmel-sysregs.txt | 6 -- .../timer/microchip,sam9x60-pit64b.yaml | 56 +++++++++++++++++++ 2 files changed, 56 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/microchip,sam9x60-pit64b.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 7024839c5da2..54d3f586403e 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -4,12 +4,6 @@ Chipid required properties: - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" - reg : Should contain registers location and length -PIT64B Timer required properties: -- compatible: Should be "microchip,sam9x60-pit64b" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for PIT64B timer -- clocks: Should contain the available clock sources for PIT64B timer. - System Timer (ST) required properties: - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" - reg: Should contain registers location and length diff --git a/Documentation/devicetree/bindings/timer/microchip,sam9x60-pit64b.yaml b/Documentation/devicetree/bindings/timer/microchip,sam9x60-pit64b.yaml new file mode 100644 index 000000000000..9378eca38138 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/microchip,sam9x60-pit64b.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/microchip,sam9x60-pit64b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip 64-bit Periodic Interval Timer (PIT64B) + +maintainers: + - Claudiu Beznea + +description: + The 64-bit periodic interval timer provides the operating system scheduler + interrupt. It is designed to offer maximum accuracy and efficient management, + even for systems with long response times. + +properties: + compatible: + const: microchip,sam9x60-pit64b + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: pclk + - const: gclk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + pit64b: timer@f0028000 { + compatible = "microchip,sam9x60-pit64b"; + reg = <0xf0028000 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names = "pclk", "gclk"; + }; + +...