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Wed, 31 May 2023 03:38:52 -0500 From: Thippeswamy Havalige To: , , , , , CC: , , , , , Thippeswamy Havalige Subject: [PATCH v4 2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Date: Wed, 31 May 2023 14:08:24 +0530 Message-ID: <20230531083825.985584-3-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230531083825.985584-1-thippeswamy.havalige@amd.com> References: <20230531083825.985584-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT066:EE_|DM6PR12MB5519:EE_ X-MS-Office365-Filtering-Correlation-Id: ba807da0-03d2-48fc-e5bd-08db61b27923 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cbXqDXLkaEedDs0ib4it9Mua3Lb33sDcf/0LbUYUdP0lHDiGZlGbZifC9Wgp9tuw2+PQfJFlZVPQYlOVU08G2suSHIiQisZr62vakHh76annbiwfiFN06u9xb9afsqjGLKoQ5WEzKx8ccLcz+WFA4Wv8jM1R5mCuZ0YPqUz10aStOHHnT4nelMZnPLAAufM7Zc8iWsiqlfsb0yo84wZIZE877XFowO7iqFMSytzcrQZMQ0Wv5/19ASXurGLgpaZNFFhVHeLM4xaQRdZPipI6K++yjXDHeEjBPRaZpPKQMj54yMvO+lWxvYO+imYoZnDUmQxSv26LU8Mqqp5GHZvVzMPc0U1S2BqkJuQ6Zzgjnplwb35aEDWWAhljCiydCemo3mZSLmtvgY6iUCVI0xnkeNXxKJOkUBwfQuNfWeBhOLqBY9yE08poARyEJqH1dA1B3SA+t8kW54/7oIIXj66eBX8ZMTnr38HCZsmg303orrs5BiLKEzlZZbMrr/mX4TFLxqyle2KiJIDwvRrixZbuKWQPqCK/xjkX32G1AWdW7p/VzGt4LPoeLf5NZACX/3UIrL+JQk1IeMjNGTyDQ1aQ5ilb+02GoZHCy8rSflHoBTECsrClFk8CANYh9mc5a/j2mE8Fa+hbSUMyUY1yyEDURY4JVLXLl4VU8GukQp1OpOpQbx6bSP6nX+vTRx644OH6l9VGW3k7UqfPbtlJuPjqj1cQ6ngVWIRmD+uNFoZye5MSoHXasqWXSXhKHpN9FNoS+NWGeM1CgBcD5+Xm/HJAOtXIavhi5MmZYhz6orisqZg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(136003)(376002)(346002)(396003)(451199021)(46966006)(36840700001)(40470700004)(1076003)(26005)(36860700001)(41300700001)(6666004)(966005)(47076005)(186003)(426003)(336012)(2616005)(110136005)(54906003)(40460700003)(478600001)(82740400003)(70586007)(70206006)(356005)(4326008)(316002)(40480700001)(5660300002)(8936002)(82310400005)(81166007)(44832011)(8676002)(2906002)(36756003)(86362001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2023 08:38:56.6119 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba807da0-03d2-48fc-e5bd-08db61b27923 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5519 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230531_013905_527345_427BD23F X-CRM114-Status: GOOD ( 14.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add YAML dtschemas of Xilinx XDMA Soft IP PCIe Root Port Bridge dt binding. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada Reviewed-by: Krzysztof Kozlowski --- change in v4: - Removed unnecessary space. changes in v3: - Fixed compatible string issue. - Modified ranges property description to maxItems. - Modified address-cell property of interrupt-controller child node. changes in v2: - None .../bindings/pci/xlnx,xdma-host.yaml | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml new file mode 100644 index 000000000000..94f17a394110 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx XDMA PL PCIe Root Port Bridge + +maintainers: + - Thippeswamy Havalige + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: xlnx,xdma-host-3.00 + + reg: + maxItems: 1 + + ranges: + maxItems: 2 + + interrupts: + items: + - description: interrupt asserted when miscellaneous interrupt is received. + - description: msi0 interrupt asserted when an MSI is received. + - description: msi1 interrupt asserted when an MSI is received. + + interrupt-names: + items: + - const: misc + - const: msi0 + - const: msi1 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + interrupt-map: + maxItems: 4 + + "#interrupt-cells": + const: 1 + + interrupt-controller: + description: identifies the node as an interrupt controller + type: object + properties: + interrupt-controller: true + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + required: + - interrupt-controller + - "#address-cells" + - "#interrupt-cells" + + additionalProperties: false + +required: + - compatible + - reg + - ranges + - interrupts + - interrupt-map + - interrupt-map-mask + - "#interrupt-cells" + - interrupt-controller + +unevaluatedProperties: false + +examples: + + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie@a0000000 { + compatible = "xlnx,xdma-host-3.00"; + reg = <0x0 0xa0000000 0x0 0x10000000>; + ranges = <0x2000000 0x0 0xB0000000 0x0 0xB0000000 0x0 0x1000000>, + <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = , , + ; + interrupt-names = "misc", "msi0", "msi1"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + pcie_intc_0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + };