| Message ID | 20230602183515.3778780-1-nfraprado@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: mediatek: mt8192: Fix CPUs capacity-dmips-mhz | expand |
Il 02/06/23 20:35, Nícolas F. R. A. Prado ha scritto: > The capacity-dmips-mhz parameter was miscalculated: this SoC runs > the first (Cortex-A55) cluster at a maximum of 2000MHz and the > second (Cortex-A76) cluster at a maximum of 2200MHz. > > In order to calculate the right capacity-dmips-mhz, the following > test was performed: > 1. CPUFREQ governor was set to 'performance' on both clusters > 2. Ran dhrystone with 500000000 iterations for 10 times on each cluster > 3. Calculated the mean result for each cluster > 4. Calculated DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz > 5. Scaled results to 1024: > result_c0 = dmips_mhz_c0 / dmips_mhz_c1 * 1024 > > The mean results for this SoC are: > Cluster 0 (LITTLE): 12016411 Dhry/s > Cluster 1 (BIG): 31702034 Dhry/s > > The calculated scaled results are: > Cluster 0: 426.953226899238 (rounded to 427) > Cluster 1: 1024 > > Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile") > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On 05/06/2023 10:21, AngeloGioacchino Del Regno wrote: > Il 02/06/23 20:35, Nícolas F. R. A. Prado ha scritto: >> The capacity-dmips-mhz parameter was miscalculated: this SoC runs >> the first (Cortex-A55) cluster at a maximum of 2000MHz and the >> second (Cortex-A76) cluster at a maximum of 2200MHz. >> >> In order to calculate the right capacity-dmips-mhz, the following >> test was performed: >> 1. CPUFREQ governor was set to 'performance' on both clusters >> 2. Ran dhrystone with 500000000 iterations for 10 times on each cluster >> 3. Calculated the mean result for each cluster >> 4. Calculated DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz >> 5. Scaled results to 1024: >> result_c0 = dmips_mhz_c0 / dmips_mhz_c1 * 1024 >> >> The mean results for this SoC are: >> Cluster 0 (LITTLE): 12016411 Dhry/s >> Cluster 1 (BIG): 31702034 Dhry/s >> >> The calculated scaled results are: >> Cluster 0: 426.953226899238 (rounded to 427) >> Cluster 1: 1024 >> >> Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board >> dts and Makefile") >> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> >> > Applied, thanks > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > >
On Tue, Jun 06, 2023 at 08:38:42AM +0200, Matthias Brugger wrote: > > > On 05/06/2023 10:21, AngeloGioacchino Del Regno wrote: > > Il 02/06/23 20:35, Nícolas F. R. A. Prado ha scritto: > > > The capacity-dmips-mhz parameter was miscalculated: this SoC runs > > > the first (Cortex-A55) cluster at a maximum of 2000MHz and the > > > second (Cortex-A76) cluster at a maximum of 2200MHz. > > > > > > In order to calculate the right capacity-dmips-mhz, the following > > > test was performed: > > > 1. CPUFREQ governor was set to 'performance' on both clusters > > > 2. Ran dhrystone with 500000000 iterations for 10 times on each cluster > > > 3. Calculated the mean result for each cluster > > > 4. Calculated DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz > > > 5. Scaled results to 1024: > > > result_c0 = dmips_mhz_c0 / dmips_mhz_c1 * 1024 > > > > > > The mean results for this SoC are: > > > Cluster 0 (LITTLE): 12016411 Dhry/s > > > Cluster 1 (BIG): 31702034 Dhry/s > > > > > > The calculated scaled results are: > > > Cluster 0: 426.953226899238 (rounded to 427) > > > Cluster 1: 1024 > > > > > > Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and > > > evaluation board dts and Makefile") > > > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > > > > > > > Applied, thanks Hi Matthias, this patch doesn't show in your v6.4-next/dts64 branch, while the other patch you just applied does, so I just wanted to double check it was really applied. Thanks, Nícolas
On 06/06/2023 15:00, Nícolas F. R. A. Prado wrote: > On Tue, Jun 06, 2023 at 08:38:42AM +0200, Matthias Brugger wrote: >> >> >> On 05/06/2023 10:21, AngeloGioacchino Del Regno wrote: >>> Il 02/06/23 20:35, Nícolas F. R. A. Prado ha scritto: >>>> The capacity-dmips-mhz parameter was miscalculated: this SoC runs >>>> the first (Cortex-A55) cluster at a maximum of 2000MHz and the >>>> second (Cortex-A76) cluster at a maximum of 2200MHz. >>>> >>>> In order to calculate the right capacity-dmips-mhz, the following >>>> test was performed: >>>> 1. CPUFREQ governor was set to 'performance' on both clusters >>>> 2. Ran dhrystone with 500000000 iterations for 10 times on each cluster >>>> 3. Calculated the mean result for each cluster >>>> 4. Calculated DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz >>>> 5. Scaled results to 1024: >>>> result_c0 = dmips_mhz_c0 / dmips_mhz_c1 * 1024 >>>> >>>> The mean results for this SoC are: >>>> Cluster 0 (LITTLE): 12016411 Dhry/s >>>> Cluster 1 (BIG): 31702034 Dhry/s >>>> >>>> The calculated scaled results are: >>>> Cluster 0: 426.953226899238 (rounded to 427) >>>> Cluster 1: 1024 >>>> >>>> Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and >>>> evaluation board dts and Makefile") >>>> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> >>>> >>> >> >> Applied, thanks > > Hi Matthias, > > this patch doesn't show in your v6.4-next/dts64 branch, while the other patch > you just applied does, so I just wanted to double check it was really applied. > I forgot to push it, should be fixed now. Regards, Matthias
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 63247c832f42..db17f67bb801 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -71,7 +71,7 @@ cpu0: cpu@0 { d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; - capacity-dmips-mhz = <530>; + capacity-dmips-mhz = <427>; }; cpu1: cpu@100 { @@ -89,7 +89,7 @@ cpu1: cpu@100 { d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; - capacity-dmips-mhz = <530>; + capacity-dmips-mhz = <427>; }; cpu2: cpu@200 { @@ -107,7 +107,7 @@ cpu2: cpu@200 { d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; - capacity-dmips-mhz = <530>; + capacity-dmips-mhz = <427>; }; cpu3: cpu@300 { @@ -125,7 +125,7 @@ cpu3: cpu@300 { d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; - capacity-dmips-mhz = <530>; + capacity-dmips-mhz = <427>; }; cpu4: cpu@400 {
The capacity-dmips-mhz parameter was miscalculated: this SoC runs the first (Cortex-A55) cluster at a maximum of 2000MHz and the second (Cortex-A76) cluster at a maximum of 2200MHz. In order to calculate the right capacity-dmips-mhz, the following test was performed: 1. CPUFREQ governor was set to 'performance' on both clusters 2. Ran dhrystone with 500000000 iterations for 10 times on each cluster 3. Calculated the mean result for each cluster 4. Calculated DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz 5. Scaled results to 1024: result_c0 = dmips_mhz_c0 / dmips_mhz_c1 * 1024 The mean results for this SoC are: Cluster 0 (LITTLE): 12016411 Dhry/s Cluster 1 (BIG): 31702034 Dhry/s The calculated scaled results are: Cluster 0: 426.953226899238 (rounded to 427) Cluster 1: 1024 Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)