From patchwork Tue Jun 6 15:35:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 13269397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E7F4C77B73 for ; Tue, 6 Jun 2023 15:36:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=AeXuPi8LgwjxrIceVdB0lZjt8oANw4hVCq9l1yzYD3Y=; b=F1+de/D1XTXt7D CyUQ+KSJoxUKgJv7ZGhalL+aI6sZguuaTXnZ/FuNBH5trKvf0j+dfdsbJgcLNvCYOMt9RxptBsSRS JqnkrIXkhtcQNdYNrYdevq4o5mPNgbX1WkhOBxIFIH6D0EB5A1bRpKV7wRlOlbbXtO0BTVA9nr3T9 4CkB4NNkO6hHC2gcijvFMt5Om3QnH5P35+vdulGAI4VsDB3ykTr7x6dQbzC8yXAGsmMhP2NQscbcR /U1UVMOw5VezcjbypU6NH3UcSugMfwCNAEW9N4QJ4igsOi4O02UmCJZHfCo0SJcHhTj3fqIXNm9ZT hrhbkj9oaoDsbJvUb+jQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6Yj5-002GXG-0F; Tue, 06 Jun 2023 15:36:03 +0000 Received: from finn.gateworks.com ([108.161.129.64] helo=finn.localdomain) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q6Yj2-002GWN-1x for linux-arm-kernel@lists.infradead.org; Tue, 06 Jun 2023 15:36:01 +0000 Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1q6Yiv-0067o3-6V; Tue, 06 Jun 2023 15:35:53 +0000 From: Tim Harvey To: linux-arm-kernel@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Li Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tim Harvey Subject: [PATCH] arm64: dts: imx8m{m,n}-venice-gw7902: add SDR50/SDR104 SDIO support for wifi Date: Tue, 6 Jun 2023 08:35:50 -0700 Message-Id: <20230606153550.1449000-1-tharvey@gateworks.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230606_083600_648281_3062EC62 X-CRM114-Status: GOOD ( 10.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The GW7902 has a Murata LBEE5H 802.11abgnac / BT5 module based on the Cypress CYW43455 which supports SDR50/SDR104. Add dt pinctrl for the 100mhz and 200mhz states to support SDR50/SDR104. While at it add the dt node for the CYW43455 wifi. Signed-off-by: Tim Harvey --- .../dts/freescale/imx8mm-venice-gw7902.dts | 33 ++++++++++++++++++- .../dts/freescale/imx8mn-venice-gw7902.dts | 33 ++++++++++++++++++- 2 files changed, 64 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index c33ec6826d32..1ae9c72705cc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -714,12 +714,21 @@ &usbotg2 { /* SDIO WiFi */ &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; bus-width = <4>; non-removable; vmmc-supply = <®_wifi>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + wifi@0 { + compatible = "brcm,bcm43455-fmac"; + reg = <0>; + }; }; /* eMMC */ @@ -992,6 +1001,28 @@ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 >; }; + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 7c12518dbc96..f80217e8df99 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -667,12 +667,21 @@ &usbotg1 { /* SDIO WiFi */ &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; bus-width = <4>; non-removable; vmmc-supply = <®_wifi>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + wifi@0 { + compatible = "brcm,bcm43455-fmac"; + reg = <0>; + }; }; /* eMMC */ @@ -923,6 +932,28 @@ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 >; }; + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190