| Message ID | 20230607-topic-amlogic-upstream-clkid-public-migration-v1-12-9676afa6b22c@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: meson: move all private clk IDs to public dt-bindings headers | expand |
On Wed, Jun 07, 2023 at 12:56:23PM +0200, Neil Armstrong wrote: > Due to a policy change in clock ID bindings handling, expose > all the "private" clock IDs to the public clock dt-bindings > to move out of the previous maintenance scheme. > > This refers to a discussion at [1] & [2] with Krzysztof about > the issue with the current maintenance. > > It was decided to move every A1 pll ID to the public clock > dt-bindings headers to be merged in a single tree so we > can safely add new clocks without having merge issues. > > [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ > [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > drivers/clk/meson/a1-pll.h | 15 --------------- > include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 5 +++++ > 2 files changed, 5 insertions(+), 15 deletions(-) > > diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h > index 82570759e6a2..0add1c7ea9f5 100644 > --- a/drivers/clk/meson/a1-pll.h > +++ b/drivers/clk/meson/a1-pll.h > @@ -28,19 +28,4 @@ > /* include the CLKIDs that have been made part of the DT binding */ > #include <dt-bindings/clock/amlogic,a1-pll-clkc.h> > > -/* > - * CLKID index values for internal clocks > - * > - * These indices are entirely contrived and do not map onto the hardware. > - * It has now been decided to expose everything by default in the DT header: > - * include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want > - * to expose, such as the internal muxes and dividers of composite clocks, > - * will remain defined here. > - */ > -#define CLKID_FIXED_PLL_DCO 0 > -#define CLKID_FCLK_DIV2_DIV 2 > -#define CLKID_FCLK_DIV3_DIV 3 > -#define CLKID_FCLK_DIV5_DIV 4 > -#define CLKID_FCLK_DIV7_DIV 5 > - > #endif /* __A1_PLL_H */ > diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h > index 01fb8164ac29..2b660c0f2c9f 100644 > --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h > +++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h > @@ -10,7 +10,12 @@ > #ifndef __A1_PLL_CLKC_H > #define __A1_PLL_CLKC_H > > +#define CLKID_FIXED_PLL_DCO 0 > #define CLKID_FIXED_PLL 1 > +#define CLKID_FCLK_DIV2_DIV 2 > +#define CLKID_FCLK_DIV3_DIV 3 > +#define CLKID_FCLK_DIV5_DIV 4 > +#define CLKID_FCLK_DIV7_DIV 5 > #define CLKID_FCLK_DIV2 6 > #define CLKID_FCLK_DIV3 7 > #define CLKID_FCLK_DIV5 8 > > -- > 2.34.1 > Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h index 82570759e6a2..0add1c7ea9f5 100644 --- a/drivers/clk/meson/a1-pll.h +++ b/drivers/clk/meson/a1-pll.h @@ -28,19 +28,4 @@ /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/amlogic,a1-pll-clkc.h> -/* - * CLKID index values for internal clocks - * - * These indices are entirely contrived and do not map onto the hardware. - * It has now been decided to expose everything by default in the DT header: - * include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want - * to expose, such as the internal muxes and dividers of composite clocks, - * will remain defined here. - */ -#define CLKID_FIXED_PLL_DCO 0 -#define CLKID_FCLK_DIV2_DIV 2 -#define CLKID_FCLK_DIV3_DIV 3 -#define CLKID_FCLK_DIV5_DIV 4 -#define CLKID_FCLK_DIV7_DIV 5 - #endif /* __A1_PLL_H */ diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h index 01fb8164ac29..2b660c0f2c9f 100644 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h @@ -10,7 +10,12 @@ #ifndef __A1_PLL_CLKC_H #define __A1_PLL_CLKC_H +#define CLKID_FIXED_PLL_DCO 0 #define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2_DIV 2 +#define CLKID_FCLK_DIV3_DIV 3 +#define CLKID_FCLK_DIV5_DIV 4 +#define CLKID_FCLK_DIV7_DIV 5 #define CLKID_FCLK_DIV2 6 #define CLKID_FCLK_DIV3 7 #define CLKID_FCLK_DIV5 8
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every A1 pll ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/ [2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- drivers/clk/meson/a1-pll.h | 15 --------------- include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 5 +++++ 2 files changed, 5 insertions(+), 15 deletions(-)