From patchwork Wed Jun 7 19:45:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13271197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDB8AC77B7A for ; Wed, 7 Jun 2023 19:46:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=ArzdjUQv70laY/JbryR9wrABaJIt71WBtdlDoUHAjdY=; b=t5NF8K/0fNq4AQGaFb3Kxop2yk cSPKVSl3TbXjmSR9PnR+CoLINTvDD5jU/7RPBORcq3NCFiFFXVLOGd60ap2nvaNWiSFFGNe96SK0n D03QEbxNh8DsCZonZ7KNhpJePgeraQsvTzkFtNjrMA3+FW4106T+Kpfp5rvmwGocJm4I4VhzmJMxO YK6lN36n6xbQ9DvhQvmM4/u/hQV9rVGVtYP9kzpRugiASoTpAO4H+3FoLMzA4IdWLxJdsfjq21oOn u9EDNItfC1aQf6Dvv5LhwkBfoUfBVQmlCtIxOuc0r0vmtAf3rAxLW1OQCcs7O//4T/FuQ1Zn07zWn ioKP1dIg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6z6o-0070Yl-0c; Wed, 07 Jun 2023 19:46:18 +0000 Received: from mail-pg1-x549.google.com ([2607:f8b0:4864:20::549]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q6z6f-0070US-1i for linux-arm-kernel@lists.infradead.org; Wed, 07 Jun 2023 19:46:10 +0000 Received: by mail-pg1-x549.google.com with SMTP id 41be03b00d2f7-53f84f75bf4so2618815a12.3 for ; Wed, 07 Jun 2023 12:46:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1686167166; x=1688759166; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Kt9Re8VhD2+c+e08bfchTfKK01Rj2MUePQIf0sCv4Xg=; b=qnLVcf4LBOV1GocAfKmE7OOXWzG9JXsx+o5fD5NyUihLa4ZmEEtGXBCpzgiwnDFzpW 3i9IE5h6ihvg8wwHtLHRzRrmvSiqyq53LJ5VdfHiV/e3LDQnWSjiBl2omUAEyOSXHCvb CHDx0jkRuYbIVXezwbq9YBlEropjp33Q5X5v8O3ixEuMOEQeQ8f1dVDxgyOFKJPD+e8v 8eqaxzIAlQKYECNoDAZ2EDzO7PmAJgcbwIXx6TA6P1gNq8IfNTK8hknyk2zzl5/syfVP N64VmdmpBXc9YSc4MaxWzquMO6VleuSWpfh2cPXzcRKY2zF8umgZx0vTVuieF++qHdj4 q5Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686167166; x=1688759166; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Kt9Re8VhD2+c+e08bfchTfKK01Rj2MUePQIf0sCv4Xg=; b=G7ixnExZp/mlo0nKVZbmza+fog+68SKWQZ4W47QAjEKM99hwp+zhNF7jH8yM302fad dpGk0QFzSEASWhpc9aytoax/8DMNFYcIgfV7+IYoYG/Xs1xLOEmcnoj375qyIAnti1j1 dMLFbPfWva35xjtDunEuOsEqxMPH3Co0JIw/HoDoukTaOy6gO8oM/hAKvTkFp5BIz7zJ TYjb8UBX8JiPxI80eb1pQkmoSOhDazESbXiupfBxerLTxUo+fM6NuIk+UMHgU/53K7vY 8OdwJCR+UbKldWih3dT25NX8NPRBP5CthjrFUeczWAU0vTah/MkMSdI4K2ysitNHb1XV zHkA== X-Gm-Message-State: AC+VfDymC7AqdbS3SvWT+ttXPHa/9Nez3qzzavdNbgJEyrTMr0BirrOm qKbQRvsLkIPxFVOWj4HAcOew7JDQJc9GLvf8MA== X-Google-Smtp-Source: ACHHUZ6AdZhHVsK3gBqZ29mngq3wYJzUe8nyFBCy0MXmvWuiKLwI//W+KPq7fWqN45t7RWSqbJlvv7QNt3JQHgOuqw== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a17:902:db02:b0:1b0:4af9:9032 with SMTP id m2-20020a170902db0200b001b04af99032mr2121642plx.0.1686167165934; Wed, 07 Jun 2023 12:46:05 -0700 (PDT) Date: Wed, 7 Jun 2023 19:45:54 +0000 In-Reply-To: <20230607194554.87359-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230607194554.87359-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230607194554.87359-5-jingzhangos@google.com> Subject: [PATCH v4 4/4] KVM: arm64: Enable writable for ID_AA64MMFR{0, 1, 2}_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Jing Zhang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230607_124609_570686_35FCC04F X-CRM114-Status: GOOD ( 13.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable writable from userspace for ID_AA64MMFR{0, 1, 2}_EL1. Added a macro for defining general writable idregs. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 36 ++++++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 8f3ad9c12b27..54c762c95983 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1391,9 +1391,6 @@ static u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu, u32 encoding) val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), pmuver_to_perfmon(vcpu_pmuver(vcpu))); break; - case SYS_ID_AA64MMFR2_EL1: - val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; - break; case SYS_ID_MMFR4_EL1: val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); break; @@ -1663,6 +1660,18 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, return pmuver_update(vcpu, rd, val, perfmon_to_pmuver(perfmon), valid_pmu); } +static u64 read_sanitised_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + u64 val; + u32 id = reg_to_encoding(rd); + + val = read_sanitised_ftr_reg(id); + val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; + + return val; +} + /* * cpufeature ID register user accessors * @@ -1898,6 +1907,16 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, .val = 0, \ } +#define ID_SANITISED_WRITABLE(name) { \ + SYS_DESC(SYS_##name), \ + .access = access_id_reg, \ + .get_user = get_id_reg, \ + .set_user = set_id_reg, \ + .visibility = id_visibility, \ + .reset = general_read_kvm_sanitised_reg,\ + .val = GENMASK(63, 0), \ +} + /* sys_reg_desc initialiser for known cpufeature ID registers */ #define AA32_ID_SANITISED(name) { \ SYS_DESC(SYS_##name), \ @@ -2113,9 +2132,14 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_UNALLOCATED(6,7), /* CRm=7 */ - ID_SANITISED(ID_AA64MMFR0_EL1), - ID_SANITISED(ID_AA64MMFR1_EL1), - ID_SANITISED(ID_AA64MMFR2_EL1), + ID_SANITISED_WRITABLE(ID_AA64MMFR0_EL1), + ID_SANITISED_WRITABLE(ID_AA64MMFR1_EL1), + { SYS_DESC(SYS_ID_AA64MMFR2_EL1), + .access = access_id_reg, + .get_user = get_id_reg, + .set_user = set_id_reg, + .reset = read_sanitised_id_aa64mmfr2_el1, + .val = GENMASK(63, 0), }, ID_UNALLOCATED(7,3), ID_UNALLOCATED(7,4), ID_UNALLOCATED(7,5),