@@ -3,6 +3,10 @@
#ifndef __SOC_MEDIATEK_MT8188_MMSYS_H
#define __SOC_MEDIATEK_MT8188_MMSYS_H
+#include <dt-bindings/reset/mt8188-resets.h>
+
+#define MT8188_VDO0_SW0_RST_B 0x190
+
#define MT8188_VDO0_OVL_MOUT_EN 0xf14
#define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
#define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
@@ -118,6 +122,28 @@
#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
#define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c
+static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
+ [MT8188_VDO0_RST_DISP_OVL0] = 0,
+ [MT8188_VDO0_RST_FAKE_ENG0] = 2,
+ [MT8188_VDO0_RST_DISP_CCORR0] = 4,
+ [MT8188_VDO0_RST_DISP_MUTEX0] = 6,
+ [MT8188_VDO0_RST_DISP_GAMMA0] = 8,
+ [MT8188_VDO0_RST_DISP_DITHER0] = 10,
+ [MT8188_VDO0_RST_DISP_WDMA0] = 17,
+ [MT8188_VDO0_RST_DISP_RDMA0] = 19,
+ [MT8188_VDO0_RST_DSI0] = 21,
+ [MT8188_VDO0_RST_DSI1] = 22,
+ [MT8188_VDO0_RST_DSC_WRAP0] = 23,
+ [MT8188_VDO0_RST_VPP_MERGE0] = 24,
+ [MT8188_VDO0_RST_DP_INTF0] = 25,
+ [MT8188_VDO0_RST_DISP_AAL0] = 26,
+ [MT8188_VDO0_RST_INLINEROT0] = 27,
+ [MT8188_VDO0_RST_APB_BUS] = 28,
+ [MT8188_VDO0_RST_DISP_COLOR0] = 29,
+ [MT8188_VDO0_RST_MDP_WROT0] = 30,
+ [MT8188_VDO0_RST_DISP_RSZ0] = 31,
+};
+
static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -87,6 +87,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
.clk_driver = "clk-mt8188-vdo0",
.routes = mmsys_mt8188_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
+ .sw0_rst_offset = MT8188_VDO0_SW0_RST_B,
+ .rst_tb = mmsys_mt8188_vdo0_rst_tb,
+ .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb),
};
static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
Add MT8188 VDO0 reset bit map. Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> --- drivers/soc/mediatek/mt8188-mmsys.h | 26 ++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 3 +++ 2 files changed, 29 insertions(+) -- 2.18.0