Message ID | 20230616105827.21656-1-zajec5@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | ARM: dts: BCM5301X: Add cells sizes to PCIe nodes | expand |
From: Florian Fainelli <f.fainelli@gmail.com> On Fri, 16 Jun 2023 12:58:27 +0200, Rafał Miłecki <zajec5@gmail.com> wrote: > From: Rafał Miłecki <rafal@milecki.pl> > > This fixes: > arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@12000: '#address-cells' is a required property > From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml > arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@12000: '#size-cells' is a required property > From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml > arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@13000: '#address-cells' is a required property > From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml > arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@13000: '#size-cells' is a required property > From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml > arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@14000: '#address-cells' is a required property > From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml > arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@14000: '#size-cells' is a required property > From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml > > Two properties that need to be added later are "device_type" and > "ranges". Adding "device_type" on its own causes a new warning and the > value of "ranges" needs to be determined yet. > > Signed-off-by: Rafał Miłecki <rafal@milecki.pl> > --- Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! -- Florian
diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi index 53472d376a2c..dae9c47ace76 100644 --- a/arch/arm/boot/dts/bcm-ns.dtsi +++ b/arch/arm/boot/dts/bcm-ns.dtsi @@ -176,14 +176,23 @@ chipcommon: chipcommon@0 { pcie0: pcie@12000 { reg = <0x00012000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; }; pcie1: pcie@13000 { reg = <0x00013000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; }; pcie2: pcie@14000 { reg = <0x00014000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; }; usb2: usb2@21000 {