| Message ID | 20230616174050.644880-1-pankaj.gupta@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/9] arm64: dts: imx8ulp-evk: add caam jr | expand |
Just a single patch? or this belongs to a patchset? Regards, Peng. On 6/17/2023 1:40 AM, Pankaj Gupta wrote: > > > Add crypto node in device tree for: > - CAAM job-ring > > Signed-off-by: Varun Sethi <v.sethi@nxp.com> > Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 32 ++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > index 32193a43ff49..ce8de81cac9a 100644 > --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > @@ -207,6 +207,38 @@ pcc3: clock-controller@292d0000 { > #reset-cells = <1>; > }; > > + crypto: crypto@292e0000 { > + compatible = "fsl,sec-v4.0"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x292e0000 0x10000>; > + ranges = <0 0x292e0000 0x10000>; > + > + sec_jr0: jr@1000 { > + compatible = "fsl,sec-v4.0-job-ring"; > + reg = <0x1000 0x1000>; > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + sec_jr1: jr@2000 { > + compatible = "fsl,sec-v4.0-job-ring"; > + reg = <0x2000 0x1000>; > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + sec_jr2: jr@3000 { > + compatible = "fsl,sec-v4.0-job-ring"; > + reg = <0x3000 0x1000>; > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + sec_jr3: jr@4000 { > + compatible = "fsl,sec-v4.0-job-ring"; > + reg = <0x4000 0x1000>; > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > tpm5: tpm@29340000 { > compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; > reg = <0x29340000 0x1000>; > -- > 2.34.1 >
Hi Peng, It is the single patch. I have re-send this patch with correct subject. Regards Pankaj > -----Original Message----- > From: Peng Fan (OSS) <peng.fan@oss.nxp.com> > Sent: Monday, June 26, 2023 6:56 AM > To: Pankaj Gupta <pankaj.gupta@nxp.com>; robh+dt@kernel.org; > krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; > shawnguo@kernel.org; s.hauer@pengutronix.de; kernel@pengutronix.de; > festevam@gmail.com; dl-linux-imx <linux-imx@nxp.com>; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Cc: Varun Sethi <V.Sethi@nxp.com> > Subject: Re: [PATCH 1/9] arm64: dts: imx8ulp-evk: add caam jr > > Just a single patch? or this belongs to a patchset? > > Regards, > Peng. > > On 6/17/2023 1:40 AM, Pankaj Gupta wrote: > > > > > > Add crypto node in device tree for: > > - CAAM job-ring > > > > Signed-off-by: Varun Sethi <v.sethi@nxp.com> > > Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 32 > ++++++++++++++++++++++ > > 1 file changed, 32 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > > index 32193a43ff49..ce8de81cac9a 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > > @@ -207,6 +207,38 @@ pcc3: clock-controller@292d0000 { > > #reset-cells = <1>; > > }; > > > > + crypto: crypto@292e0000 { > > + compatible = "fsl,sec-v4.0"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + reg = <0x292e0000 0x10000>; > > + ranges = <0 0x292e0000 0x10000>; > > + > > + sec_jr0: jr@1000 { > > + compatible = "fsl,sec-v4.0-job-ring"; > > + reg = <0x1000 0x1000>; > > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + sec_jr1: jr@2000 { > > + compatible = "fsl,sec-v4.0-job-ring"; > > + reg = <0x2000 0x1000>; > > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + sec_jr2: jr@3000 { > > + compatible = "fsl,sec-v4.0-job-ring"; > > + reg = <0x3000 0x1000>; > > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + > > + sec_jr3: jr@4000 { > > + compatible = "fsl,sec-v4.0-job-ring"; > > + reg = <0x4000 0x1000>; > > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + }; > > + > > tpm5: tpm@29340000 { > > compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; > > reg = <0x29340000 0x1000>; > > -- > > 2.34.1 > >
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 32193a43ff49..ce8de81cac9a 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -207,6 +207,38 @@ pcc3: clock-controller@292d0000 { #reset-cells = <1>; }; + crypto: crypto@292e0000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x292e0000 0x10000>; + ranges = <0 0x292e0000 0x10000>; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr3: jr@4000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x4000 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + tpm5: tpm@29340000 { compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; reg = <0x29340000 0x1000>;