| Message ID | 20230703124647.215952-7-alexghiti@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: Allow userspace to directly access perf counters | expand |
On Mon, Jul 3, 2023 at 5:52 AM Alexandre Ghiti <alexghiti@rivosinc.com> wrote: > > Implement the needed callbacks in the legacy driver so that we can > directly access the counters through perf in userspace. > > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > --- > drivers/perf/riscv_pmu_legacy.c | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c > index 6a000abc28bb..79fdd667922e 100644 > --- a/drivers/perf/riscv_pmu_legacy.c > +++ b/drivers/perf/riscv_pmu_legacy.c > @@ -71,6 +71,29 @@ static void pmu_legacy_ctr_start(struct perf_event *event, u64 ival) > local64_set(&hwc->prev_count, initial_val); > } > > +static uint8_t pmu_legacy_csr_index(struct perf_event *event) > +{ > + return event->hw.idx; > +} > + > +static void pmu_legacy_event_mapped(struct perf_event *event, struct mm_struct *mm) > +{ > + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && > + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) > + return; > + > + event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; > +} > + > +static void pmu_legacy_event_unmapped(struct perf_event *event, struct mm_struct *mm) > +{ > + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && > + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) > + return; > + > + event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT; > +} > + > /* > * This is just a simple implementation to allow legacy implementations > * compatible with new RISC-V PMU driver framework. > @@ -91,6 +114,9 @@ static void pmu_legacy_init(struct riscv_pmu *pmu) > pmu->ctr_get_width = NULL; > pmu->ctr_clear_idx = NULL; > pmu->ctr_read = pmu_legacy_read_ctr; > + pmu->event_mapped = pmu_legacy_event_mapped; > + pmu->event_unmapped = pmu_legacy_event_unmapped; > + pmu->csr_index = pmu_legacy_csr_index; > > perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW); > } > -- > 2.39.2 > Reviewed-by: Atish Patra <atishp@rivosinc.com>
diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c index 6a000abc28bb..79fdd667922e 100644 --- a/drivers/perf/riscv_pmu_legacy.c +++ b/drivers/perf/riscv_pmu_legacy.c @@ -71,6 +71,29 @@ static void pmu_legacy_ctr_start(struct perf_event *event, u64 ival) local64_set(&hwc->prev_count, initial_val); } +static uint8_t pmu_legacy_csr_index(struct perf_event *event) +{ + return event->hw.idx; +} + +static void pmu_legacy_event_mapped(struct perf_event *event, struct mm_struct *mm) +{ + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) + return; + + event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; +} + +static void pmu_legacy_event_unmapped(struct perf_event *event, struct mm_struct *mm) +{ + if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && + event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) + return; + + event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT; +} + /* * This is just a simple implementation to allow legacy implementations * compatible with new RISC-V PMU driver framework. @@ -91,6 +114,9 @@ static void pmu_legacy_init(struct riscv_pmu *pmu) pmu->ctr_get_width = NULL; pmu->ctr_clear_idx = NULL; pmu->ctr_read = pmu_legacy_read_ctr; + pmu->event_mapped = pmu_legacy_event_mapped; + pmu->event_unmapped = pmu_legacy_event_unmapped; + pmu->csr_index = pmu_legacy_csr_index; perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW); }