| Message ID | 20230705104815.511400-1-xu.yang_2@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] perf/imx_ddr: speed up overflow frequency of cycle counter | expand |
> + > + /* > + * Workaround for i.MX8MP: > + * Common counters and byte counters share the same > COUNTER_CNTL, > + * and byte counters could overflow before cycle counter. > Need set > + * counter parameter(CP) of cycle counter to give it initial > value > + * which can speed up cycle counter overflow frequency. > + */ > + if ((pmu->devtype_data->quirks & > DDR_CAP_AXI_ID_FILTER_ENHANCED) == > + DDR_CAP_AXI_ID_FILTER_ENHANCED) { needn't `==` if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) Did you fixed cycle counter also? Dose cycle counter read get correct value? Frank > + if (counter == EVENT_CYCLES_COUNTER) > + val |= FIELD_PREP(CNTL_CP_MASK, 0xf0); > + } > + > writel(val, pmu->base + reg); > } else { > /* Disable counter */ > -- > 2.34.1
Hi Frank, > -----Original Message----- > From: Frank Li <frank.li@nxp.com> > Sent: Wednesday, July 5, 2023 10:57 PM > To: Xu Yang <xu.yang_2@nxp.com> > Cc: will@kernel.org; mark.rutland@arm.com; shawnguo@kernel.org; s.hauer@pengutronix.de; kernel@pengutronix.de; > dl-linux-imx <linux-imx@nxp.com>; linux-arm-kernel@lists.infradead.org > Subject: RE: [PATCH 1/3] perf/imx_ddr: speed up overflow frequency of cycle counter > > > + > > + /* > > + * Workaround for i.MX8MP: > > + * Common counters and byte counters share the same > > COUNTER_CNTL, > > + * and byte counters could overflow before cycle counter. > > Need set > > + * counter parameter(CP) of cycle counter to give it initial > > value > > + * which can speed up cycle counter overflow frequency. > > + */ > > + if ((pmu->devtype_data->quirks & > > DDR_CAP_AXI_ID_FILTER_ENHANCED) == > > + DDR_CAP_AXI_ID_FILTER_ENHANCED) { > > needn't `==` > if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) No, this workaround is only for imx8mp. We need this condition to filter it. > > Did you fixed cycle counter also? Dose cycle counter read get correct value? Does cycle counter has some issues? I have tested it and can get correct value from cycle counter. Thanks, Xu Yang > > Frank > > > + if (counter == EVENT_CYCLES_COUNTER) > > + val |= FIELD_PREP(CNTL_CP_MASK, 0xf0); > > + } > > + > > writel(val, pmu->base + reg); > > } else { > > /* Disable counter */ > > -- > > 2.34.1
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 5222ba1e79d0..cc7693f49950 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -28,6 +28,8 @@ #define CNTL_CLEAR_MASK 0xFFFFFFFD #define CNTL_OVER_MASK 0xFFFFFFFE +#define CNTL_CP_SHIFT 16 +#define CNTL_CP_MASK (0xFF << CNTL_CP_SHIFT) #define CNTL_CSV_SHIFT 24 #define CNTL_CSV_MASK (0xFFU << CNTL_CSV_SHIFT) @@ -427,6 +429,20 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, writel(0, pmu->base + reg); val = CNTL_EN | CNTL_CLEAR; val |= FIELD_PREP(CNTL_CSV_MASK, config); + + /* + * Workaround for i.MX8MP: + * Common counters and byte counters share the same COUNTER_CNTL, + * and byte counters could overflow before cycle counter. Need set + * counter parameter(CP) of cycle counter to give it initial value + * which can speed up cycle counter overflow frequency. + */ + if ((pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) == + DDR_CAP_AXI_ID_FILTER_ENHANCED) { + if (counter == EVENT_CYCLES_COUNTER) + val |= FIELD_PREP(CNTL_CP_MASK, 0xf0); + } + writel(val, pmu->base + reg); } else { /* Disable counter */
For i.MX8MP, we cannot ensure that cycle counter overflow occurs at least 4 times as often as other events. Due to byte counters will count for any event configured, it will overflow more often. And if byte counters overflow that related counters would stop since they share the COUNTER_CNTL. We can speed up cycle counter overflow frequency by setting counter parameter (CP) field of cycle counter. In this way, we can avoid stop counting byte counters when interrupt didn't come and the byte counters can be fetched or updated from each cycle counter overflow interrupt. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> --- drivers/perf/fsl_imx8_ddr_perf.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)