| Message ID | 20230712121219.2654234-3-pankaj.gupta@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | firmware: imx: NXP Edgelock Enclave MUAP Driver | expand |
On 12/07/2023 14:12, Pankaj Gupta wrote: > Added support for NXP secure enclave called EdgeLock Enclave > firmware (se-fw) for imx8ulp-evk. > > Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > index 3ddc0f3125b3..10ed31974a6f 100644 > --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > @@ -114,7 +114,7 @@ sosc: clock-sosc { > #clock-cells = <0>; > }; > > - sram@2201f000 { > + sram0: sram@2201f000 { > compatible = "mmio-sram"; > reg = <0x0 0x2201f000 0x0 0x1000>; > > @@ -161,6 +161,16 @@ s4muap: mailbox@27020000 { > #mbox-cells = <2>; > }; > > + ele_fw: se-fw { > + compatible = "fsl,imx-ele"; > + mboxes = <&s4muap 0 0 &s4muap 1 0>; > + mbox-names = "tx", "rx"; > + fsl,mu-did = <7>; > + fsl,mu-id = <2>; > + sram-pool = <&sram0>; It does not look like you tested the DTS against bindings. Please run `make dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). > + status = "okay"; It's by default. Best regards, Krzysztof
> -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Sent: Thursday, July 13, 2023 12:08 AM > To: Pankaj Gupta <pankaj.gupta@nxp.com>; shawnguo@kernel.org; > s.hauer@pengutronix.de; kernel@pengutronix.de; clin@suse.com; > conor+dt@kernel.org; pierre.gondois@arm.com; Jacky Bai > <ping.bai@nxp.com>; Clark Wang <xiaoning.wang@nxp.com>; Wei Fang > <wei.fang@nxp.com>; Peng Fan <peng.fan@nxp.com>; Bough Chen > <haibo.chen@nxp.com>; festevam@gmail.com; dl-linux-imx <linux- > imx@nxp.com>; davem@davemloft.net; robh+dt@kernel.org; > krzysztof.kozlowski+dt@linaro.org; linux-arm-kernel@lists.infradead.org; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Gaurav Jain > <gaurav.jain@nxp.com>; alexander.stein@ew.tq-group.com; Sahil Malhotra > <sahil.malhotra@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com>; Varun > Sethi <V.Sethi@nxp.com> > Subject: [EXT] Re: [PATCH v4 2/7] arm64: dts: imx8ulp-evk: added nxp secure > enclave firmware > > Caution: This is an external email. Please take care when clicking links or > opening attachments. When in doubt, report the message using the 'Report > this email' button > > > On 12/07/2023 14:12, Pankaj Gupta wrote: > > Added support for NXP secure enclave called EdgeLock Enclave firmware > > (se-fw) for imx8ulp-evk. > > > > Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 12 +++++++++++- > > 1 file changed, 11 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > > b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > > index 3ddc0f3125b3..10ed31974a6f 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > > @@ -114,7 +114,7 @@ sosc: clock-sosc { > > #clock-cells = <0>; > > }; > > > > - sram@2201f000 { > > + sram0: sram@2201f000 { > > compatible = "mmio-sram"; > > reg = <0x0 0x2201f000 0x0 0x1000>; > > > > @@ -161,6 +161,16 @@ s4muap: mailbox@27020000 { > > #mbox-cells = <2>; > > }; > > > > + ele_fw: se-fw { > > + compatible = "fsl,imx-ele"; > > + mboxes = <&s4muap 0 0 &s4muap 1 0>; > > + mbox-names = "tx", "rx"; > > + fsl,mu-did = <7>; > > + fsl,mu-id = <2>; > > + sram-pool = <&sram0>; > > It does not look like you tested the DTS against bindings. Please run `make > dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst or > https://www.li/ > naro.org%2Fblog%2Ftips-and-tricks-for-validating-devicetree-sources-with- > the-devicetree- > schema%2F&data=05%7C01%7Cpankaj.gupta%40nxp.com%7Cd13d0b68d01c > 4d10d8cb08db83070ed2%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0% > 7C0%7C638247838553225400%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC > 4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7 > C%7C%7C&sdata=pO6dnz4aPqVejRNDR0OU4n04hXebyqgrNKg4DPhahI0%3D > &reserved=0 > for instructions). Tested. Before submitting the patch. [Pankaj] Accepted. > > > + status = "okay"; > > It's by default. > Will be removed from the V5. > Best regards, > Krzysztof
On 08/08/2023 13:07, Pankaj Gupta wrote: > > >> -----Original Message----- >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> Sent: Thursday, July 13, 2023 12:08 AM >> To: Pankaj Gupta <pankaj.gupta@nxp.com>; shawnguo@kernel.org; >> s.hauer@pengutronix.de; kernel@pengutronix.de; clin@suse.com; >> conor+dt@kernel.org; pierre.gondois@arm.com; Jacky Bai >> <ping.bai@nxp.com>; Clark Wang <xiaoning.wang@nxp.com>; Wei Fang >> <wei.fang@nxp.com>; Peng Fan <peng.fan@nxp.com>; Bough Chen >> <haibo.chen@nxp.com>; festevam@gmail.com; dl-linux-imx <linux- >> imx@nxp.com>; davem@davemloft.net; robh+dt@kernel.org; >> krzysztof.kozlowski+dt@linaro.org; linux-arm-kernel@lists.infradead.org; >> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Gaurav Jain >> <gaurav.jain@nxp.com>; alexander.stein@ew.tq-group.com; Sahil Malhotra >> <sahil.malhotra@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com>; Varun >> Sethi <V.Sethi@nxp.com> >> Subject: [EXT] Re: [PATCH v4 2/7] arm64: dts: imx8ulp-evk: added nxp secure >> enclave firmware >> >> Caution: This is an external email. Please take care when clicking links or >> opening attachments. When in doubt, report the message using the 'Report >> this email' button >> >> >> On 12/07/2023 14:12, Pankaj Gupta wrote: >>> Added support for NXP secure enclave called EdgeLock Enclave firmware >>> (se-fw) for imx8ulp-evk. >>> >>> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> >>> --- >>> arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 12 +++++++++++- >>> 1 file changed, 11 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi >>> b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi >>> index 3ddc0f3125b3..10ed31974a6f 100644 >>> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi >>> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi >>> @@ -114,7 +114,7 @@ sosc: clock-sosc { >>> #clock-cells = <0>; >>> }; >>> >>> - sram@2201f000 { >>> + sram0: sram@2201f000 { >>> compatible = "mmio-sram"; >>> reg = <0x0 0x2201f000 0x0 0x1000>; >>> >>> @@ -161,6 +161,16 @@ s4muap: mailbox@27020000 { >>> #mbox-cells = <2>; >>> }; >>> >>> + ele_fw: se-fw { >>> + compatible = "fsl,imx-ele"; >>> + mboxes = <&s4muap 0 0 &s4muap 1 0>; >>> + mbox-names = "tx", "rx"; >>> + fsl,mu-did = <7>; >>> + fsl,mu-id = <2>; >>> + sram-pool = <&sram0>; >> >> It does not look like you tested the DTS against bindings. Please run `make >> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst or >> https://www.li/ >> naro.org%2Fblog%2Ftips-and-tricks-for-validating-devicetree-sources-with- >> the-devicetree- >> schema%2F&data=05%7C01%7Cpankaj.gupta%40nxp.com%7Cd13d0b68d01c >> 4d10d8cb08db83070ed2%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0% >> 7C0%7C638247838553225400%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC >> 4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7 >> C%7C%7C&sdata=pO6dnz4aPqVejRNDR0OU4n04hXebyqgrNKg4DPhahI0%3D >> &reserved=0 >> for instructions). > > Tested. Before submitting the patch. > [Pankaj] Accepted. You really tested that patch? Before I waste my time on proving it was not, are you 100% sure that you tested that patch and no new warnings are printed? Or are you just agreeing with me that this time you will test? > Best regards, Krzysztof
> -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Sent: Tuesday, August 8, 2023 8:19 PM > To: Pankaj Gupta <pankaj.gupta@nxp.com>; shawnguo@kernel.org; > s.hauer@pengutronix.de; kernel@pengutronix.de; clin@suse.com; > conor+dt@kernel.org; pierre.gondois@arm.com; Jacky Bai > <ping.bai@nxp.com>; Clark Wang <xiaoning.wang@nxp.com>; Wei Fang > <wei.fang@nxp.com>; Peng Fan <peng.fan@nxp.com>; Bough Chen > <haibo.chen@nxp.com>; festevam@gmail.com; dl-linux-imx <linux- > imx@nxp.com>; davem@davemloft.net; robh+dt@kernel.org; > krzysztof.kozlowski+dt@linaro.org; linux-arm-kernel@lists.infradead.org; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Gaurav Jain > <gaurav.jain@nxp.com>; alexander.stein@ew.tq-group.com; Sahil Malhotra > <sahil.malhotra@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com>; > Varun Sethi <V.Sethi@nxp.com> > Subject: Re: [EXT] Re: [PATCH v4 2/7] arm64: dts: imx8ulp-evk: added nxp > secure enclave firmware > > Caution: This is an external email. Please take care when clicking links or > opening attachments. When in doubt, report the message using the 'Report > this email' button > > > On 08/08/2023 13:07, Pankaj Gupta wrote: > > > > > >> -----Original Message----- > >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > >> Sent: Thursday, July 13, 2023 12:08 AM > >> To: Pankaj Gupta <pankaj.gupta@nxp.com>; shawnguo@kernel.org; > >> s.hauer@pengutronix.de; kernel@pengutronix.de; clin@suse.com; > >> conor+dt@kernel.org; pierre.gondois@arm.com; Jacky Bai > >> <ping.bai@nxp.com>; Clark Wang <xiaoning.wang@nxp.com>; Wei Fang > >> <wei.fang@nxp.com>; Peng Fan <peng.fan@nxp.com>; Bough Chen > >> <haibo.chen@nxp.com>; festevam@gmail.com; dl-linux-imx <linux- > >> imx@nxp.com>; davem@davemloft.net; robh+dt@kernel.org; > >> krzysztof.kozlowski+dt@linaro.org; > >> linux-arm-kernel@lists.infradead.org; > >> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Gaurav Jain > >> <gaurav.jain@nxp.com>; alexander.stein@ew.tq-group.com; Sahil > >> Malhotra <sahil.malhotra@nxp.com>; Aisheng Dong > >> <aisheng.dong@nxp.com>; Varun Sethi <V.Sethi@nxp.com> > >> Subject: [EXT] Re: [PATCH v4 2/7] arm64: dts: imx8ulp-evk: added nxp > >> secure enclave firmware > >> > >> Caution: This is an external email. Please take care when clicking > >> links or opening attachments. When in doubt, report the message using > >> the 'Report this email' button > >> > >> > >> On 12/07/2023 14:12, Pankaj Gupta wrote: > >>> Added support for NXP secure enclave called EdgeLock Enclave > >>> firmware > >>> (se-fw) for imx8ulp-evk. > >>> > >>> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> > >>> --- > >>> arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 12 +++++++++++- > >>> 1 file changed, 11 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > >>> b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > >>> index 3ddc0f3125b3..10ed31974a6f 100644 > >>> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > >>> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi > >>> @@ -114,7 +114,7 @@ sosc: clock-sosc { > >>> #clock-cells = <0>; > >>> }; > >>> > >>> - sram@2201f000 { > >>> + sram0: sram@2201f000 { > >>> compatible = "mmio-sram"; > >>> reg = <0x0 0x2201f000 0x0 0x1000>; > >>> > >>> @@ -161,6 +161,16 @@ s4muap: mailbox@27020000 { > >>> #mbox-cells = <2>; > >>> }; > >>> > >>> + ele_fw: se-fw { > >>> + compatible = "fsl,imx-ele"; > >>> + mboxes = <&s4muap 0 0 &s4muap 1 0>; > >>> + mbox-names = "tx", "rx"; > >>> + fsl,mu-did = <7>; > >>> + fsl,mu-id = <2>; > >>> + sram-pool = <&sram0>; > >> > >> It does not look like you tested the DTS against bindings. Please run > >> `make dtbs_check` (see > >> Documentation/devicetree/bindings/writing-schema.rst or > >> Following tests (1 &2) were performed: 1. make -j32. Build the images and DTB to test the functionality. 2. make dt_binding_check DT_SCHEMA_FILES=freescale. 3. make CHECK_DTBS=y freescale/imx8ulp-evk.dtb Before sending the V4 patch for review, I have ran tests 1 &2. Both were passing. But after seeing the page shared by you, ran the 3rd test and I was able to reproduce the issue, you might be referring to. For V5, I will perform all the 3 tests. > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fww > w > >> .li%2F&data=05%7C01%7Cpankaj.gupta%40nxp.com%7Cfce997832862 > 4056830408 > >> > db981e9af6%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6382 > 710294401 > >> > 41352%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2 > luMzIiLCJ > >> > BTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=Ki%2BHqff7 > rZbTAnAbJ > >> ZgRiwxGUx0qJjYzxIjMHNoyM8s%3D&reserved=0 > >> naro.org%2Fblog%2Ftips-and-tricks-for-validating-devicetree-sources-w > >> ith- > >> the-devicetree- > >> > schema%2F&data=05%7C01%7Cpankaj.gupta%40nxp.com%7Cd13d0b68d0 > 1c > >> > 4d10d8cb08db83070ed2%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0% > >> > 7C0%7C638247838553225400%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiM > C > >> > 4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000 > %7 > >> > C%7C%7C&sdata=pO6dnz4aPqVejRNDR0OU4n04hXebyqgrNKg4DPhahI0%3 > D > >> &reserved=0 > >> for instructions). > > > > Tested. Before submitting the patch. > > [Pankaj] Accepted. > > You really tested that patch? Before I waste my time on proving it was not, > are you 100% sure that you tested that patch and no new warnings are > printed? Or are you just agreeing with me that this time you will test? > > > > Best regards, > Krzysztof
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 3ddc0f3125b3..10ed31974a6f 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -114,7 +114,7 @@ sosc: clock-sosc { #clock-cells = <0>; }; - sram@2201f000 { + sram0: sram@2201f000 { compatible = "mmio-sram"; reg = <0x0 0x2201f000 0x0 0x1000>; @@ -161,6 +161,16 @@ s4muap: mailbox@27020000 { #mbox-cells = <2>; }; + ele_fw: se-fw { + compatible = "fsl,imx-ele"; + mboxes = <&s4muap 0 0 &s4muap 1 0>; + mbox-names = "tx", "rx"; + fsl,mu-did = <7>; + fsl,mu-id = <2>; + sram-pool = <&sram0>; + status = "okay"; + }; + per_bridge3: bus@29000000 { compatible = "simple-bus"; reg = <0x29000000 0x800000>;
Added support for NXP secure enclave called EdgeLock Enclave firmware (se-fw) for imx8ulp-evk. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)