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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: aAiIPmHOdsrvaWZkkgRuoExrV2NXHE+sTjPLOgEHhJGEDrDr1+BpSDZCFnXeBps+FIHL0Ol5CYYLeVYIB/R6xLWpYSept0hxLfhqzXgEs+xD26ckok6XEJwf5F8KFCJWNnGCuGu3ZGGNfREtw/LYHGRY+PZsJPu8Lcll8rPD5DYFJJnVBsqZZejaHGJjCuBXnzTluV/jbP4GBFRPztjOOCxiMt2hIkxDosFNVm3pVSfGrTsSPioqyh5wb8JJ9T6m+KkoGg26eBvAZfUrGTD1MimJyMdyQCITVInUxKedAgBFyMogl41leql9tM2NroRZnBMhpErvncvMxb92xa54w2YNc54YlYwxxlCYV47dJOv0E9rGeyBHyZ0xlXlJoAORShUIGkOATxVaf4Wtjpp9/y+cA9Y+u4o6xW8KHI9sKxrWy8UF8Cr1irojdyIY5gCvP1mGeOukVFvz3/DNFpxxZC6WB+2AR1QcRMC82/9ZXYblVFlMhFNzx63lQkOgptwMlyaYRA8pLQu/+hZeFNPW3vst9crMv1Y49NftLJkxa62G2z8xOId9lQ92ZG6Ag8djENzJa2SIf4WQZsQU6nr2w9JR/qGsNG3ld4rRbrLGvw9lMujTA9OLLdzJ1uCyXFPnYXiKiP+YE2eWxyeWGZ24utKJeHn2mafMBbJPTzSbjw4XFfBaLA6pu2tLz3+pwElDCAkXTImz5aBe2kbwh4ToZVS66k+6ZlIwPlMxsdz93b90FZUvqvLX6xiMAcX4+CUW71v4lZsbHb7UhcGh7uxVddTOCsZgPGgFC0V0Sk3XnJ27RTxkABtfURP5f5BRnK/eBjuwrDKH9c5GqHd35fTshCV5ieAqTkZMjIVoEm+laT2JyPAarigvJAcpWF8JwJsWCFsp60Xqahxx7EiLpwIeVdq2ad6QS9feRLWQHFFtq3DWbLxcd3VXt//aXInvwEaFL+uNicBpPRJemZUDTde+G6FloMJ5wcKmn4OvxL5rR9GfNWE1OmfraQoGDbLNZ8dvO5ru0Z7hZWpSY/FuuUjvMJv+qmbPySelisa2kCV/Yx4bp6ooz2HB8T64NoTG8OKJ5PxAdObOs4fN8j70F5JBTAnBSH/+Z0PxKQC/7QA1aQ5N46zlDHOgVpNKQSnvfDy4Ex3jDKPLixInwNEsvVudpHllDuPZnCmS1DCQGoDcu196PqMZVeOIwgs1FW0HAK+9phB791T1k3lF/+inz0Y++7Gf7QjecRbgVHbKS0U4nUMh2JPgWCAGZ/ZxEykpC8cxqqbKhcYWLycaznSWS4H2DbiFOYaFlOqivm8sow1IlWikOWUovJGOlECzidhIeGtWmpP21AIuMFktN8K955sMnWtkJpeFIFVXD5sArCtoH+lJ80joqBsryoDwiB1cnOzPXp+RcO5gLbcTMBswvIj1x7Lgl2upHDdUO3sespab4OaUgmWvT/GI0JcSJOAdoqwCeYBDbC8grS4TL4S441jxC5z+gqY0fEpXx3H8LbN5nuqJNnJmSvAf4vmB5AaIvGmxxPPL/7VP8LaA0RVL8S+AI83vorW9sqDu38aQc7pHcTkbiLYcsOPHaBYwI38wTxIMl0zDaG6LSjVCb8ZIiOFtOA== X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8d4e5565-fa4b-4140-e6ec-08db8405fe6f X-MS-Exchange-CrossTenant-AuthSource: DM5PR0102MB3590.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2023 01:02:28.3131 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0r5Na3f7pflSwPBg19EXTN0hoi8jCjxaIe/1ZLQis4y4IMMll4xudE6oxnPiC2tQfGar8xIAE6aJjAFOYn0UQe7MAhUFq0Z2/OX5wsyRyZ96di49QOct+uGLCq0i9qq5 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY3PR01MB6611 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230713_180235_765576_FA2C670A X-CRM114-Status: GOOD ( 13.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org ARM Coresight PMU architecture specification [1] defines PMEVTYPER and PMEVFILT* registers as optional in Chapter 2.1. Moreover, implementers may choose to use PMIMPDEF* registers (offset: 0xD80-> 0xDFF) to filter the events. Add support for those by adding implementation specific filter callback function. [1] https://developer.arm.com/documentation/ihi0091/latest Signed-off-by: Ilkka Koskinen Reviewed-by: Besar Wicaksono --- drivers/perf/arm_cspmu/arm_cspmu.c | 8 ++++++-- drivers/perf/arm_cspmu/arm_cspmu.h | 3 +++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c index 0f517152cb4e..fafd734c3218 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -117,6 +117,9 @@ static unsigned long arm_cspmu_cpuhp_state; +static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, + struct hw_perf_event *hwc, u32 filter); + static struct acpi_apmt_node *arm_cspmu_apmt_node(struct device *dev) { return *(struct acpi_apmt_node **)dev_get_platdata(dev); @@ -426,6 +429,7 @@ static int arm_cspmu_init_impl_ops(struct arm_cspmu *cspmu) CHECK_DEFAULT_IMPL_OPS(impl_ops, event_type); CHECK_DEFAULT_IMPL_OPS(impl_ops, event_filter); CHECK_DEFAULT_IMPL_OPS(impl_ops, event_attr_is_visible); + CHECK_DEFAULT_IMPL_OPS(impl_ops, set_ev_filter); return 0; } @@ -792,7 +796,7 @@ static inline void arm_cspmu_set_event(struct arm_cspmu *cspmu, writel(hwc->config, cspmu->base0 + offset); } -static inline void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, +static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, struct hw_perf_event *hwc, u32 filter) { @@ -826,7 +830,7 @@ static void arm_cspmu_start(struct perf_event *event, int pmu_flags) arm_cspmu_set_cc_filter(cspmu, filter); } else { arm_cspmu_set_event(cspmu, hwc); - arm_cspmu_set_ev_filter(cspmu, hwc, filter); + cspmu->impl.ops.set_ev_filter(cspmu, hwc, filter); } hwc->state = 0; diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h b/drivers/perf/arm_cspmu/arm_cspmu.h index 83df53d1c132..d6d88c246a23 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.h +++ b/drivers/perf/arm_cspmu/arm_cspmu.h @@ -101,6 +101,9 @@ struct arm_cspmu_impl_ops { u32 (*event_type)(const struct perf_event *event); /* Decode filter value from configs */ u32 (*event_filter)(const struct perf_event *event); + /* Set event filter */ + void (*set_ev_filter)(struct arm_cspmu *cspmu, + struct hw_perf_event *hwc, u32 filter); /* Hide/show unsupported events */ umode_t (*event_attr_is_visible)(struct kobject *kobj, struct attribute *attr, int unused);