From patchwork Tue Jul 18 16:45:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13318331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CECDBC001DC for ; Wed, 19 Jul 2023 06:30:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=UR92AK4+He66r/KF1BXQZg1hUnLROkT7IuSnjN3cAU0=; b=IEi5e/lo4mmQIUfX8ojNcxH7nu hlRfZv4Ed/+8u0dDQEahFOHfaoRMrBreAZiSLiboyJnTfpTCyEChr5gut9rpth+z/nQWRb1ihBTDQ Nnf5FhiF3CIWZtxmq6VbcW6opFkW/fob5WPlcCZ0Zz4X1VaGTjx9ZiER7ZeDJaEKndAROOgOEEd4V pDjPB/g9+neIZCdUX/HGCDFdXzM47AC4PLoEe6ZEo9M+i9EhDPYUeVCLM+1nGFigbQYl3ICLlqBnn 0Q8c1FVnOVWR/nW+OuYTqqgSouU8pxnmouXdW4vKg3ODR5Hh61uFyYqwsftupbR8wDcJIzBaVXbZC UDNqOSpg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qM0hZ-005kmv-1i; Wed, 19 Jul 2023 06:30:21 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qM0hW-005klP-0k for linux-arm-kernel@bombadil.infradead.org; Wed, 19 Jul 2023 06:30:18 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Type:Cc:To:From:Subject: Message-ID:References:Mime-Version:In-Reply-To:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=cSCQIj8rChbfCOl6GeXcnV+0FBKWws4kYFyMtOPVmVQ=; b=lOghUsCbxIlsKHfLmaVDjQ5DVZ tBb4Q9RDeAAkUfD6ADaisKtsnI+UMOnxenSN2Ut/PYauR1kQZGQ3vE7v1aRf2akFM+MY4h7dqVZKV Pmq03ksaF4Akb/KzoxKiSGDo8dZsgpRA0LHeV6v2V2HShU3G8gGY1nw9S0FxGYJFhkmsAG+1W9UzG bV1aA3jULCOLLLkore0LX5HJWpyTiRPcszcSdtqq3Q38Ok0hvQWZA0r+dR+AsUeku45di8jTVN0CA YJKM2G2cu3UopT0nyCdLCN3jHavAmsG6iP3niG+og8xyhpLZ7Cl5nQfOK4A2QrrJjvWUceHb20h9+ pB/9S6WQ==; Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]) by desiato.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qLnrI-00BlUU-1n for linux-arm-kernel@lists.infradead.org; Tue, 18 Jul 2023 16:47:34 +0000 Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-1b8a7735231so30851205ad.1 for ; Tue, 18 Jul 2023 09:47:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1689698731; x=1692290731; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=cSCQIj8rChbfCOl6GeXcnV+0FBKWws4kYFyMtOPVmVQ=; b=LYPlt5PCzOhzwb9jrbb1TeJjrKyo+CnqYLoLjtu7RUwIwm35AvNoNxt9ti1YGoONUN zLyopu6rgJou5cRnQQwxJwzjzVDCUPQsgLWRtG5H3DmGf+pTbTtnYEYjS9/nmd0SnQVi WuEqgoc+hy4yPwUBn7UVfPoeisRTo2Jljpwd9LAs4cBprde8U2wgWUyapgSdO/vmzDTZ kZDCy0DQAWiEu1I3NAwQC1kpRHKajYQn5llAMWcLxPYzGahRpllvuMwZTx3btJXKrXNr /bLzjohgBK/CT5D5tr7xDecygLRrJKdHua6pSeNqnQfh9f+RFDBPS6U2fAaRgiVpLIQO wgcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689698731; x=1692290731; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cSCQIj8rChbfCOl6GeXcnV+0FBKWws4kYFyMtOPVmVQ=; b=cKdVCcirf+MG4eMjL4L3/AwV6jrg2CLQ9Fje1nbZXDr3gVMy2XDm96LWVxXu4H+Mq2 VrGmrevP0hw3uMIok9kevIdRb5PDrj8hRQ1V4T+lbBXiMk8T+N4sDQafxb2dzAMwfEyG t5SbaKuINB/vXihuujnRqno2SiXzxhvA6qGFi3pm2QBFheel4YVGr7DRTVLtkiJONADp xtqyHytWsAFawlCtC/FLV/5AoPKnmu1rZO74D+9FSYA0Gu5kLBEf02Mdg8pC0yrFaGwl pC4+Sk0ZxOr1n8lIU4G6YpkVvIWKKqC7OWbTSEG+StqEtmthqZsttRtZq0+lzWo9aAyO bsZQ== X-Gm-Message-State: ABy/qLbDwmhCeFrAi7kLcBmKvui4rzy2gDCJSX6QpGpxPqAXQjzBNK/A W/tFgEyFSPII7319r8C+Fsh5uj6QQ4N8rU5OiA== X-Google-Smtp-Source: APBJJlEvf6ms5QOH822cn1EVJyhNAJK5wSXxGxatRmMDn9eETOI47IUA/zPlPUd4v3/huIcfn7gFBUTLmfU4n0bWaA== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a17:902:e812:b0:1ae:6895:cb96 with SMTP id u18-20020a170902e81200b001ae6895cb96mr1340plg.5.1689698730965; Tue, 18 Jul 2023 09:45:30 -0700 (PDT) Date: Tue, 18 Jul 2023 16:45:18 +0000 In-Reply-To: <20230718164522.3498236-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230718164522.3498236-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230718164522.3498236-3-jingzhangos@google.com> Subject: [PATCH v6 2/6] KVM: arm64: Reject attempts to set invalid debug arch version From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230718_174732_734697_1231887D X-CRM114-Status: GOOD ( 15.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Oliver Upton The debug architecture is mandatory in ARMv8, so KVM should not allow userspace to configure a vCPU with less than that. Of course, this isn't handled elegantly by the generic ID register plumbing, as the respective ID register fields have a nonzero starting value. Add an explicit check for debug versions less than v8 of the architecture. Signed-off-by: Oliver Upton Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c1a5ec1a016e..053d8057ff1e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1216,8 +1216,14 @@ static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, /* Some features have different safe value type in KVM than host features */ switch (id) { case SYS_ID_AA64DFR0_EL1: - if (kvm_ftr.shift == ID_AA64DFR0_EL1_PMUVer_SHIFT) + switch (kvm_ftr.shift) { + case ID_AA64DFR0_EL1_PMUVer_SHIFT: kvm_ftr.type = FTR_LOWER_SAFE; + break; + case ID_AA64DFR0_EL1_DebugVer_SHIFT: + kvm_ftr.type = FTR_LOWER_SAFE; + break; + } break; case SYS_ID_DFR0_EL1: if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) @@ -1469,14 +1475,22 @@ static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, return val; } +#define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ +({ \ + u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ + (val) &= ~reg##_##field##_MASK; \ + (val) |= FIELD_PREP(reg##_##field##_MASK, \ + min(__f_val, (u64)reg##_##field##_##limit)); \ + (val); \ +}) + static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); /* Limit debug to ARMv8.0 */ - val &= ~ID_AA64DFR0_EL1_DebugVer_MASK; - val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DebugVer, IMP); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8); /* * Only initialize the PMU version if the vCPU was configured with one. @@ -1496,6 +1510,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val) { + u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); /* @@ -1515,6 +1530,13 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; + /* + * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a + * nonzero minimum safe value. + */ + if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) + return -EINVAL; + return set_id_reg(vcpu, rd, val); } @@ -1528,6 +1550,8 @@ static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, if (kvm_vcpu_has_pmu(vcpu)) val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8); + return val; } @@ -1536,6 +1560,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, u64 val) { u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); + u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { val &= ~ID_DFR0_EL1_PerfMon_MASK; @@ -1551,6 +1576,9 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) return -EINVAL; + if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) + return -EINVAL; + return set_id_reg(vcpu, rd, val); }