From patchwork Sat Jul 22 07:44:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 13322849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A6E9EB64DA for ; Sat, 22 Jul 2023 07:45:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Srg2cTabljj9ZbHT7YzADv+T3FyjxN02oFN1WgsU+WE=; b=uR4sjmYEd8V4bV ++KO8c47Lhir+4VGtnAeYCZVhqggn2zBNdmF1DOCZhM7mVH9dhJAhGwt2gx7e5uGOzgOcfitB46cn dOUpdP3zucv8dnwvLi/FnA8H4wVNqs4W9k/XwbCIsk53VMmgb2V0rYZ0Ej1sIuNK+5zcb4l76NTJI /jA4I19KyTozGwPJlhU6SLF1mE4WXM5Yqv9atulxLhh0mhcYc6pH1wYgczZ6YN1Tee6J2deUsLJI5 kSVwCJcClzdkx71QoizqDQZCKCL9poIiK9tQaJPc/yi6kMyuN3S2HSX1ywbQAY6RzN3hbhRWTK4tc EpUvtn+OjHCo9cDyPMwg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qN7Ik-00G445-00; Sat, 22 Jul 2023 07:45:18 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qN7IR-00G3yy-0s; Sat, 22 Jul 2023 07:45:01 +0000 X-UUID: a6c11c50286311ee912e1518a6540028-20230722 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=TPr7sXgdlH3VNKL6uLkPjL/MuPJ8naNc1jeRgaa1pVM=; b=mKu3W6tog4ARoK668hypeRleghpDUjKMRlm4MB02V6/8N+qjA4vNw55aUWO+8IXvHcvnKuoxB74dM/iuzKTdxhnS9yaTJm5lGEovhIEU2yticENl2/nflX9AZ1HVhLdlXwQtNUrIVltanj0sbPin1dl0FxqdyPUJezWUPNW34Go=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:4f9f3c2d-e7d4-4f38-8db3-2bcc42678798,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:176cd25,CLOUDID:ad05f48e-7caa-48c2-8dbb-206f0389473c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: a6c11c50286311ee912e1518a6540028-20230722 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1898230616; Sat, 22 Jul 2023 00:44:55 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Sat, 22 Jul 2023 15:44:53 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Sat, 22 Jul 2023 15:44:52 +0800 From: Yunfei Dong To: =?utf-8?q?N=C3=ADcolas_F_=2E_R_=2E_A_=2E_Prado?= , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert CC: Chen-Yu Tsai , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , Steve Cho , Yunfei Dong , Mingjia Zhang , , , , , , Subject: [PATCH v2,3/3] media: mediatek: vcodec: Add driver to support 10bit Date: Sat, 22 Jul 2023 15:44:48 +0800 Message-ID: <20230722074448.30671-4-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230722074448.30671-1-yunfei.dong@mediatek.com> References: <20230722074448.30671-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230722_004459_308580_E215A280 X-CRM114-Status: GOOD ( 20.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mingjia Zhang Adding to support capture formats V4L2_PIX_FMT_MT2110T and V4L2_PIX_FMT_MT2110R for 10bit playback. Need to get the size of each plane again when user space setting syntax to get 10bit information. V4L2_PIX_FMT_MT2110T for AV1/VP9/HEVC. V4L2_PIX_FMT_MT2110R for H264. Signed-off-by: Mingjia Zhang Co-developed-by: Yunfei Dong Signed-off-by: Yunfei Dong --- .../mediatek/vcodec/decoder/mtk_vcodec_dec.c | 22 ++- .../vcodec/decoder/mtk_vcodec_dec_drv.h | 5 + .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 144 +++++++++++++++++- 3 files changed, 167 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c index 5acb7dff18f2..91ed576d6821 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c @@ -37,7 +37,9 @@ static bool mtk_vdec_get_cap_fmt(struct mtk_vcodec_dec_ctx *ctx, int format_inde { const struct mtk_vcodec_dec_pdata *dec_pdata = ctx->dev->vdec_pdata; const struct mtk_video_fmt *fmt; + struct mtk_q_data *q_data; int num_frame_count = 0, i; + bool ret = false; fmt = &dec_pdata->vdec_formats[format_index]; for (i = 0; i < *dec_pdata->num_formats; i++) { @@ -47,10 +49,26 @@ static bool mtk_vdec_get_cap_fmt(struct mtk_vcodec_dec_ctx *ctx, int format_inde num_frame_count++; } - if (num_frame_count == 1 || fmt->fourcc == V4L2_PIX_FMT_MM21) + if (num_frame_count == 1 || (!ctx->is_10bit_bitstream && fmt->fourcc == V4L2_PIX_FMT_MM21)) return true; - return false; + q_data = &ctx->q_data[MTK_Q_DATA_SRC]; + switch (q_data->fmt->fourcc) { + case V4L2_PIX_FMT_H264_SLICE: + if (ctx->is_10bit_bitstream && fmt->fourcc == V4L2_PIX_FMT_MT2110R) + ret = true; + break; + case V4L2_PIX_FMT_VP9_FRAME: + case V4L2_PIX_FMT_AV1_FRAME: + case V4L2_PIX_FMT_HEVC_SLICE: + if (ctx->is_10bit_bitstream && fmt->fourcc == V4L2_PIX_FMT_MT2110T) + ret = true; + break; + default: + break; + } + + return ret; } static struct mtk_q_data *mtk_vdec_get_q_data(struct mtk_vcodec_dec_ctx *ctx, diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index aa49969c54c1..6c318de25a55 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -31,6 +31,7 @@ enum mtk_vdec_format_types { MTK_VDEC_FORMAT_AV1_FRAME = 0x800, MTK_VDEC_FORMAT_HEVC_FRAME = 0x1000, MTK_VCODEC_INNER_RACING = 0x20000, + MTK_VDEC_IS_SUPPORT_10BIT = 0x40000, }; /* @@ -160,6 +161,8 @@ struct mtk_vcodec_dec_pdata { * @hw_id: hardware index used to identify different hardware. * * @msg_queue: msg queue used to store lat buffer information. + * + * @is_10bit_bitstream: set to true if it's 10bit bitstream */ struct mtk_vcodec_dec_ctx { enum mtk_instance_type type; @@ -202,6 +205,8 @@ struct mtk_vcodec_dec_ctx { int hw_id; struct vdec_msg_queue msg_queue; + + bool is_10bit_bitstream; }; /** diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c index 99a84c7e1901..e29c9c58f3da 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c @@ -200,7 +200,7 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = { #define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls) -static struct mtk_video_fmt mtk_video_formats[7]; +static struct mtk_video_fmt mtk_video_formats[9]; static struct mtk_video_fmt default_out_format; static struct mtk_video_fmt default_cap_format; @@ -387,6 +387,138 @@ static int mtk_vdec_flush_decoder(struct mtk_vcodec_dec_ctx *ctx) return vdec_if_decode(ctx, NULL, NULL, &res_chg); } +static int mtk_vcodec_get_pic_info(struct mtk_vcodec_dec_ctx *ctx) +{ + struct mtk_q_data *q_data; + int ret = 0; + + q_data = &ctx->q_data[MTK_Q_DATA_DST]; + if (q_data->fmt->num_planes == 1) { + mtk_v4l2_vdec_err(ctx, "[%d]Error!! 10bit mode not support one plane", ctx->id); + return -EINVAL; + } + + ctx->capture_fourcc = q_data->fmt->fourcc; + ret = vdec_if_get_param(ctx, GET_PARAM_PIC_INFO, &ctx->picinfo); + if (ret) { + mtk_v4l2_vdec_err(ctx, "[%d]Error!! Get GET_PARAM_PICTURE_INFO Fail", ctx->id); + return ret; + } + + ctx->last_decoded_picinfo = ctx->picinfo; + + q_data->sizeimage[0] = ctx->picinfo.fb_sz[0]; + q_data->bytesperline[0] = ctx->picinfo.buf_w * 5 / 4; + + q_data->sizeimage[1] = ctx->picinfo.fb_sz[1]; + q_data->bytesperline[1] = ctx->picinfo.buf_w * 5 / 4; + + q_data->coded_width = ctx->picinfo.buf_w; + q_data->coded_height = ctx->picinfo.buf_h; + mtk_v4l2_vdec_dbg(1, ctx, "[%d] wxh=%dx%d pic wxh=%dx%d sz[0]=0x%x sz[1]=0x%x", + ctx->id, ctx->picinfo.buf_w, ctx->picinfo.buf_h, + ctx->picinfo.pic_w, ctx->picinfo.pic_h, + q_data->sizeimage[0], q_data->sizeimage[1]); + + return ret; +} + +static int mtk_vdec_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct mtk_vcodec_dec_ctx *ctx = ctrl_to_dec_ctx(ctrl); + struct v4l2_ctrl_h264_sps *h264; + struct v4l2_ctrl_hevc_sps *h265; + struct v4l2_ctrl_vp9_frame *frame; + struct v4l2_ctrl_av1_sequence *seq; + struct v4l2_ctrl *hdr_ctrl; + const struct mtk_vcodec_dec_pdata *dec_pdata = ctx->dev->vdec_pdata; + const struct mtk_video_fmt *fmt; + int i = 0, ret = 0; + + hdr_ctrl = ctrl; + if (!hdr_ctrl || !hdr_ctrl->p_new.p) + return -EINVAL; + + switch (hdr_ctrl->id) { + case V4L2_CID_STATELESS_H264_SPS: + h264 = (struct v4l2_ctrl_h264_sps *)hdr_ctrl->p_new.p; + + if (h264->bit_depth_chroma_minus8 == 2 && h264->bit_depth_luma_minus8 == 2) { + ctx->is_10bit_bitstream = true; + } else if (h264->bit_depth_chroma_minus8 != 0 && + h264->bit_depth_luma_minus8 != 0) { + mtk_v4l2_vdec_err(ctx, "H264: chroma_minus8:%d, luma_minus8:%d", + h264->bit_depth_chroma_minus8, + h264->bit_depth_luma_minus8); + return -EINVAL; + } + break; + case V4L2_CID_STATELESS_HEVC_SPS: + h265 = (struct v4l2_ctrl_hevc_sps *)hdr_ctrl->p_new.p; + + if (h265->bit_depth_chroma_minus8 == 2 && h265->bit_depth_luma_minus8 == 2) { + ctx->is_10bit_bitstream = true; + } else if (h265->bit_depth_chroma_minus8 != 0 && + h265->bit_depth_luma_minus8 != 0) { + mtk_v4l2_vdec_err(ctx, "HEVC: chroma_minus8:%d, luma_minus8:%d", + h265->bit_depth_chroma_minus8, + h265->bit_depth_luma_minus8); + return -EINVAL; + } + break; + case V4L2_CID_STATELESS_VP9_FRAME: + frame = (struct v4l2_ctrl_vp9_frame *)hdr_ctrl->p_new.p; + + if (frame->bit_depth == 10) { + ctx->is_10bit_bitstream = true; + } else if (frame->bit_depth != 8) { + mtk_v4l2_vdec_err(ctx, "VP9: bit_depth:%d", frame->bit_depth); + return -EINVAL; + } + break; + case V4L2_CID_STATELESS_AV1_SEQUENCE: + seq = (struct v4l2_ctrl_av1_sequence *)hdr_ctrl->p_new.p; + + if (seq->bit_depth == 10) { + ctx->is_10bit_bitstream = true; + } else if (seq->bit_depth != 8) { + mtk_v4l2_vdec_err(ctx, "AV1: bit_depth:%d", seq->bit_depth); + return -EINVAL; + } + break; + default: + mtk_v4l2_vdec_dbg(3, ctx, "Not supported to set ctrl id: 0x%x\n", hdr_ctrl->id); + return ret; + } + + if (!ctx->is_10bit_bitstream) + return ret; + + for (i = 0; i < *dec_pdata->num_formats; i++) { + fmt = &dec_pdata->vdec_formats[i]; + if (fmt->fourcc == V4L2_PIX_FMT_MT2110R && + hdr_ctrl->id == V4L2_CID_STATELESS_H264_SPS) { + ctx->q_data[MTK_Q_DATA_DST].fmt = fmt; + break; + } + + if (fmt->fourcc == V4L2_PIX_FMT_MT2110T && + (hdr_ctrl->id == V4L2_CID_STATELESS_HEVC_SPS || + hdr_ctrl->id == V4L2_CID_STATELESS_VP9_FRAME || + hdr_ctrl->id == V4L2_CID_STATELESS_AV1_SEQUENCE)) { + ctx->q_data[MTK_Q_DATA_DST].fmt = fmt; + break; + } + } + ret = mtk_vcodec_get_pic_info(ctx); + + return ret; +} + +static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl_ops = { + .s_ctrl = mtk_vdec_s_ctrl, +}; + static int mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx *ctx) { unsigned int i; @@ -399,7 +531,7 @@ static int mtk_vcodec_dec_ctrls_setup(struct mtk_vcodec_dec_ctx *ctx) for (i = 0; i < NUM_CTRLS; i++) { struct v4l2_ctrl_config cfg = mtk_stateless_controls[i].cfg; - + cfg.ops = &mtk_vcodec_dec_ctrl_ops; v4l2_ctrl_new_custom(&ctx->ctrl_hdl, &cfg, NULL); if (ctx->ctrl_hdl.error) { mtk_v4l2_vdec_err(ctx, "Adding control %d failed %d", i, @@ -466,6 +598,8 @@ static void mtk_vcodec_add_formats(unsigned int fourcc, break; case V4L2_PIX_FMT_MM21: case V4L2_PIX_FMT_MT21C: + case V4L2_PIX_FMT_MT2110T: + case V4L2_PIX_FMT_MT2110R: mtk_video_formats[count_formats].fourcc = fourcc; mtk_video_formats[count_formats].type = MTK_FMT_FRAME; mtk_video_formats[count_formats].num_planes = 2; @@ -491,6 +625,12 @@ static void mtk_vcodec_get_supported_formats(struct mtk_vcodec_dec_ctx *ctx) mtk_vcodec_add_formats(V4L2_PIX_FMT_MT21C, ctx); cap_format_count++; } + if (ctx->dev->dec_capability & MTK_VDEC_IS_SUPPORT_10BIT) { + mtk_vcodec_add_formats(V4L2_PIX_FMT_MT2110T, ctx); + cap_format_count++; + mtk_vcodec_add_formats(V4L2_PIX_FMT_MT2110R, ctx); + cap_format_count++; + } if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MM21) { mtk_vcodec_add_formats(V4L2_PIX_FMT_MM21, ctx); cap_format_count++;