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Mon, 31 Jul 2023 04:01:04 -0700 (PDT) Received: from localhost.localdomain ([49.205.243.15]) by smtp.gmail.com with ESMTPSA id t14-20020a1709028c8e00b001b1a2c14a4asm8281096plo.38.2023.07.31.04.01.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 04:01:03 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Cc: Jagan Teki , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH 11/14] ARM: dts: rockchip: rv1126: Add MIPI DSI pipeline Date: Mon, 31 Jul 2023 16:30:09 +0530 Message-Id: <20230731110012.2913742-12-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230731110012.2913742-1-jagan@edgeble.ai> References: <20230731110012.2913742-1-jagan@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230731_040104_889295_6D894F8F X-CRM114-Status: GOOD ( 12.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org MIPI DSI controller in RV1126 has integrated MIPI D-PHY V1.2 that supports up to 4 lanes with a 4Gbps transfer rate. Add MIPI DSI pipeline for Rockchip RV1126. Signed-off-by: Jagan Teki --- Cc: devicetree@vger.kernel.org Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley arch/arm/boot/dts/rockchip/rv1126.dtsi | 49 ++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index 9ccd1bad6229..512cc18762b6 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -276,6 +276,20 @@ cru: clock-controller@ff490000 { #reset-cells = <1>; }; + dsi_dphy: mipi-dphy@ff4d0000 { + compatible = "rockchip,rv1126-dsi-dphy"; + reg = <0xff4d0000 0x500>; + assigned-clocks = <&pmucru CLK_MIPIDSIPHY_REF>; + assigned-clock-rates = <24000000>; + clock-names = "ref", "pclk"; + clocks = <&pmucru CLK_MIPIDSIPHY_REF>, <&cru PCLK_DSIPHY>; + #phy-cells = <0>; + power-domains = <&power RV1126_PD_VO>; + reset-names = "apb"; + resets = <&cru SRST_DSIPHY_P>; + status = "disabled"; + }; + dmac: dma-controller@ff4e0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xff4e0000 0x4000>; @@ -420,6 +434,7 @@ vop_out_rgb: endpoint@0 { vop_out_dsi: endpoint@1 { reg = <1>; + remote-endpoint = <&dsi_in_vop>; }; }; }; @@ -435,6 +450,40 @@ vop_mmu: iommu@ffb00f00 { status = "disabled"; }; + dsi: dsi@ffb30000 { + compatible = "rockchip,rv1126-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0xffb30000 0x500>; + interrupts = ; + clock-names = "pclk"; + clocks = <&cru PCLK_DSIHOST>; + phy-names = "dphy"; + phys = <&dsi_dphy>; + power-domains = <&power RV1126_PD_VO>; + reset-names = "apb"; + resets = <&cru SRST_DSIHOST_P>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_in_vop: endpoint { + remote-endpoint = <&vop_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + gmac: ethernet@ffc40000 { compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; reg = <0xffc40000 0x4000>;