From patchwork Tue Aug 1 12:42:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 13336654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCD29C001DF for ; Tue, 1 Aug 2023 12:44:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=WWo+b/sHsr+zdUeHkM0UTftXXCgEFPkZc+h17q+h5Rc=; b=QgBpgmlYkIY/vm Ft85W3LGvztkpsfO9+FLEowQAisutlWHIayroVAHGYyqEqkEZfjI28GNXO/EY8wguTQscID/e3fjH YpiZqvmNHefWLpv3jxoSN5a+ABii5Wr34irE7TF9u9U13f1Dlh7kF52ivRJhzLA4A7toNchgIKIpp TIARFEXB3zW0AkbzsNPHwxb7UH52Zh/Sl+fT1kGPHy0e4CcF9pCwI1WDVOjYUeHsUqcnlQIcafgny T2wrvODkXxD99d/YPWZkfR2Qw2Z+EssS30+8QgewErP9Txx3ZVYkRh40J1GewH2Y4A48Y6bBsleFO au+5NnebYErlIK2DbHEQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qQojj-002Nid-0X; Tue, 01 Aug 2023 12:44:27 +0000 Received: from szxga01-in.huawei.com ([45.249.212.187]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qQojf-002NhB-1j for linux-arm-kernel@lists.infradead.org; Tue, 01 Aug 2023 12:44:25 +0000 Received: from canpemm500009.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4RFZXL0vGXzrRvv; Tue, 1 Aug 2023 20:43:14 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 1 Aug 2023 20:44:15 +0800 From: Yicong Yang To: , , , CC: <21cnbao@gmail.com>, , Subject: [PATCH v2 -mm] arm64: tlbflush: Add some comments for TLB batched flushing Date: Tue, 1 Aug 2023 20:42:03 +0800 Message-ID: <20230801124203.62164-1-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230801_054423_765578_826CA0F5 X-CRM114-Status: GOOD ( 11.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yicong Yang Add comments for arch_flush_tlb_batched_pending() and arch_tlbbatch_flush() to illustrate why only a DSB is needed. Cc: Catalin Marinas Signed-off-by: Yicong Yang Reviewed-by: Alistair Popple Reviewed-by: Catalin Marinas --- Change since v1: - Address one comment from Catalin: s/by a DSB/with a DSB/ - Add tags from Catalin and Alistair Link: https://lore.kernel.org/all/20230729131448.15531-1-yangyicong@huawei.com/ arch/arm64/include/asm/tlbflush.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 3456866c6a1d..bd1acaf7f715 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -300,11 +300,26 @@ static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *b __flush_tlb_page_nosync(mm, uaddr); } +/* + * If mprotect/munmap/etc occurs during TLB batched flushing, we need to + * synchronise all the TLBI issued with a DSB to avoid the race mentioned in + * flush_tlb_batched_pending(). + */ static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { dsb(ish); } +/* + * To support TLB batched flush for multiple pages unmapping, we only send + * the TLBI for each page in arch_tlbbatch_add_pending() and wait for the + * completion at the end in arch_tlbbatch_flush(). Since we've already issued + * TLBI for each page so only a DSB is needed to synchronise its effect on the + * other CPUs. + * + * This will save the time waiting on DSB comparing issuing a TLBI;DSB sequence + * for each page. + */ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) { dsb(ish);