| Message ID | 20230807082201.2332746-1-a.fatoum@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op | expand |
> Subject: [PATCH v2] clk: imx: composite-8m: fix clock pauses when set_rate > would be a no-op > > Reconfiguring the clock divider to the exact same value is observed on an > i.MX8MN to often cause a longer than usual clock pause, probably because > the divider restarts counting whenever the register is rewritten. > > This issue doesn't show up normally, because the clock framework will take > care to not call set_rate when the clock rate is the same. > However, when we reconfigure an upstream clock, the common code will > call set_rate with the newly calculated rate on all children, e.g.: > > - sai5 is running normally and divides Audio PLL out by 16. > - Audio PLL rate is increased by 32Hz (glitch-free kdiv change) > - rates for children are recalculated and rates are set recursively > - imx8m_clk_composite_divider_set_rate(sai5) is called with > 32/16 = 2Hz more > - imx8m_clk_composite_divider_set_rate computes same divider as before > - divider register is written, so it restarts counting from zero and > MCLK is briefly paused, so instead of e.g. 40ns, MCLK is low for 120ns. > > Some external clock consumers can be upset by such unexpected clock > pauses, so let's make sure we only rewrite the divider value when the value > to be written is actually different. > > Fixes: d3ff9728134e ("clk: imx: Add imx composite clock") > Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Regards, Peng.
On Mon, 07 Aug 2023 10:22:00 +0200, Ahmad Fatoum wrote: > Reconfiguring the clock divider to the exact same value is observed > on an i.MX8MN to often cause a longer than usual clock pause, probably > because the divider restarts counting whenever the register is rewritten. > > This issue doesn't show up normally, because the clock framework will > take care to not call set_rate when the clock rate is the same. > However, when we reconfigure an upstream clock, the common code will > call set_rate with the newly calculated rate on all children, e.g.: > > [...] Applied, thanks! [1/1] clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op commit: 4dd432d985ef258e3bc436e568fba4b987b59171 Best regards,
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index cbf0d7955a00..3e9a092e136c 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -97,7 +97,7 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, int prediv_value; int div_value; int ret; - u32 val; + u32 orig, val; ret = imx8m_clk_composite_compute_dividers(rate, parent_rate, &prediv_value, &div_value); @@ -106,13 +106,15 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, spin_lock_irqsave(divider->lock, flags); - val = readl(divider->reg); - val &= ~((clk_div_mask(divider->width) << divider->shift) | - (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); + orig = readl(divider->reg); + val = orig & ~((clk_div_mask(divider->width) << divider->shift) | + (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); val |= (u32)(prediv_value - 1) << divider->shift; val |= (u32)(div_value - 1) << PCG_DIV_SHIFT; - writel(val, divider->reg); + + if (val != orig) + writel(val, divider->reg); spin_unlock_irqrestore(divider->lock, flags);
Reconfiguring the clock divider to the exact same value is observed on an i.MX8MN to often cause a longer than usual clock pause, probably because the divider restarts counting whenever the register is rewritten. This issue doesn't show up normally, because the clock framework will take care to not call set_rate when the clock rate is the same. However, when we reconfigure an upstream clock, the common code will call set_rate with the newly calculated rate on all children, e.g.: - sai5 is running normally and divides Audio PLL out by 16. - Audio PLL rate is increased by 32Hz (glitch-free kdiv change) - rates for children are recalculated and rates are set recursively - imx8m_clk_composite_divider_set_rate(sai5) is called with 32/16 = 2Hz more - imx8m_clk_composite_divider_set_rate computes same divider as before - divider register is written, so it restarts counting from zero and MCLK is briefly paused, so instead of e.g. 40ns, MCLK is low for 120ns. Some external clock consumers can be upset by such unexpected clock pauses, so let's make sure we only rewrite the divider value when the value to be written is actually different. Fixes: d3ff9728134e ("clk: imx: Add imx composite clock") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> --- v1 -> v2: - replace glitch with clock pause instead (Peng) - describe how bug triggers in more detail (Peng) --- drivers/clk/imx/clk-composite-8m.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)