From patchwork Mon Aug 7 16:22:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13344528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66CE4C001DB for ; Mon, 7 Aug 2023 16:23:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=fm6jm5UI6qk1D0yVBcVIxoQ0q9KmjqRcP36yIlKez80=; b=kloJpBgAhuOqiMqMn1S979ofYr Fu2akcgxZlMBZ5DEtLMENcwNseRHy2rqein+MZ5OMNjWZCxJ9OTH/m1QCGlJ7W5ObI8I1x2/dBiPk rWfg0uv8An7XlFIMrCnDLUGEGJJPGxtK+0XS3IGInTjhffZbDqcBTsW37Chd/oeXzhRVzZhgYFKkV QX2U2Bafeb3kZRhffSBSQ+zLLfFazSRPKf1klQLFTQR1euoWZMM11qfOkpcNPUNoaSScnbh/SMRlI qCuDFDe1WtC/pIfU1v/bjfjPhLgYg/Ac8y0nKFiAdi+0w53o6R4Dn6FCBmJGzahjN87kadenBXMAb oxJ4plIw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qT30F-000Aai-0o; Mon, 07 Aug 2023 16:22:43 +0000 Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qT303-000ASY-2P for linux-arm-kernel@lists.infradead.org; Mon, 07 Aug 2023 16:22:33 +0000 Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-d4e1be2dd10so2449143276.0 for ; Mon, 07 Aug 2023 09:22:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1691425349; x=1692030149; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=ATBSjF6qBqdfdnd8w2mF20Dlf6Vur3R3tLd+6Z/cyMs=; b=i1eNS32wMwVyxs4WKb9JGC7F2FXkcX+IHurd54K2c03M6iCgApXHP/+RKzyS+vv9kJ KOn62RNuqlSIEMtJcGRrj97bkcJdDhxmkiTBjmvykmIEfhfS2APKbtyCwxuYaemi8/+r REjk8j/3KhEZALMyBaCBZWMV6Z17y2flSpLpiZM/IRcLJ6EtpxURNEyJUs1YxOnkPUD4 jLoMqWjnSwLseg5pRypEjfwZmRVeN1FEDMu3FOUKren26JqSnQ6KrrvNoXjjNx7dgRH+ eOBmxABe/GWihxsBandBo6jAJ5IxtTXfA1qiWdaSY9e/f/6rrdGQtxWPx3M3e0Gt+2Zy K6gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691425349; x=1692030149; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ATBSjF6qBqdfdnd8w2mF20Dlf6Vur3R3tLd+6Z/cyMs=; b=CjJV2Lzdtg10cOwpr4sTzNnG5/V3LSpPAzS43AmQ7l/+I3riqPu8jwJTMPp/69FCiq bdAkp2t/8l9GnRXChF3roei8oWENEB8/ICtgaVPjBY/wU2QPimoY7mT4zBymAj11WiSa xRt63lcZMqWeShNdL/5xTaM0B5QDuIfPZXi+yUdAZZ7S52n4kZPv2f9fJ2z1qPaCpDcW RpKmEorH8n7Eluh1opg4Fi/xAzjEEjrTOrL2qLjjdBuLeD88/wLsQhy0Pm6EK2tyHK/R VqY9yIynincODtSIS4QBS5cg1BGvFGjvlYyHc0YQik2AEgyWDnZwNLGtugzeTnea3X4s OnhQ== X-Gm-Message-State: AOJu0Yz6MK/fsLBtYYWlrEhJ7WossERFv2D85GXC03qYfl2ihv3jjCfo Y/B1oZtYHVjCUQ6kO5lSnFINASnF51AqOHgouA== X-Google-Smtp-Source: AGHT+IHshu44rw+o8SIUK+hYUQLk5w4Kgcs1lJhicK+bcq3hGbMtuNeTuBpA8+ho5ibjdKGHRmegILAIqvRMvxhB1w== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a25:23d6:0:b0:d4c:f456:d54f with SMTP id j205-20020a2523d6000000b00d4cf456d54fmr32913ybj.8.1691425349461; Mon, 07 Aug 2023 09:22:29 -0700 (PDT) Date: Mon, 7 Aug 2023 09:22:06 -0700 In-Reply-To: <20230807162210.2528230-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230807162210.2528230-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230807162210.2528230-9-jingzhangos@google.com> Subject: [PATCH v8 08/11] KVM: arm64: Refactor helper Macros for idreg desc From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230807_092231_787240_BDAF2C34 X-CRM114-Status: GOOD ( 13.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add some helpers to ease the declaration for idreg desc. These Macros will be heavily used for future commits enabling writable for idregs. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 79 ++++++++++++++++----------------------- 1 file changed, 33 insertions(+), 46 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 392613bec560..85b5312bdee6 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1844,27 +1844,37 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, * from userspace. */ -/* sys_reg_desc initialiser for known cpufeature ID registers */ -#define ID_SANITISED(name) { \ - SYS_DESC(SYS_##name), \ - .access = access_id_reg, \ - .get_user = get_id_reg, \ - .set_user = set_id_reg, \ - .visibility = id_visibility, \ - .reset = kvm_read_sanitised_id_reg, \ - .val = 0, \ +#define ID_DESC(name, _set_user, _visibility, _reset, mask) { \ + SYS_DESC(SYS_##name), \ + .access = access_id_reg, \ + .get_user = get_id_reg, \ + .set_user = _set_user, \ + .visibility = _visibility, \ + .reset = _reset, \ + .val = mask, \ } /* sys_reg_desc initialiser for known cpufeature ID registers */ -#define AA32_ID_SANITISED(name) { \ - SYS_DESC(SYS_##name), \ - .access = access_id_reg, \ - .get_user = get_id_reg, \ - .set_user = set_id_reg, \ - .visibility = aa32_id_visibility, \ - .reset = kvm_read_sanitised_id_reg, \ - .val = 0, \ -} +#define _ID_SANITISED(name, _set_user, _reset) \ + ID_DESC(name, _set_user, id_visibility, _reset, 0) +#define ID_SANITISED(name) \ + _ID_SANITISED(name, set_id_reg, kvm_read_sanitised_id_reg) + +#define _ID_SANITISED_W(name, _set_user, _reset) \ + ID_DESC(name, _set_user, id_visibility, _reset, GENMASK(63, 0)) +#define ID_SANITISED_W(name) \ + _ID_SANITISED_W(name, set_id_reg, kvm_read_sanitised_id_reg) + +/* sys_reg_desc initialiser for known cpufeature ID registers */ +#define _AA32_ID_SANITISED(name, _set_user, _reset) \ + ID_DESC(name, _set_user, aa32_id_visibility, _reset, 0) +#define AA32_ID_SANITISED(name) \ + _AA32_ID_SANITISED(name, set_id_reg, kvm_read_sanitised_id_reg) + +#define _AA32_ID_SANITISED_W(name, _set_user, _reset) \ + ID_DESC(name, _set_user, aa32_id_visibility, _reset, GENMASK(63, 0)) +#define AA32_ID_SANITISED_W(name) \ + _AA32_ID_SANITISED_W(name, set_id_reg, kvm_read_sanitised_id_reg) /* * sys_reg_desc initialiser for architecturally unallocated cpufeature ID @@ -1886,15 +1896,8 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, * For now, these are exposed just like unallocated ID regs: they appear * RAZ for the guest. */ -#define ID_HIDDEN(name) { \ - SYS_DESC(SYS_##name), \ - .access = access_id_reg, \ - .get_user = get_id_reg, \ - .set_user = set_id_reg, \ - .visibility = raz_visibility, \ - .reset = kvm_read_sanitised_id_reg, \ - .val = 0, \ -} +#define ID_HIDDEN(name) \ + ID_DESC(name, set_id_reg, raz_visibility, kvm_read_sanitised_id_reg, 0) static bool access_sp_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, @@ -2001,13 +2004,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* CRm=1 */ AA32_ID_SANITISED(ID_PFR0_EL1), AA32_ID_SANITISED(ID_PFR1_EL1), - { SYS_DESC(SYS_ID_DFR0_EL1), - .access = access_id_reg, - .get_user = get_id_reg, - .set_user = set_id_dfr0_el1, - .visibility = aa32_id_visibility, - .reset = read_sanitised_id_dfr0_el1, - .val = GENMASK(63, 0), }, + _AA32_ID_SANITISED_W(ID_DFR0_EL1, set_id_dfr0_el1, read_sanitised_id_dfr0_el1), ID_HIDDEN(ID_AFR0_EL1), AA32_ID_SANITISED(ID_MMFR0_EL1), AA32_ID_SANITISED(ID_MMFR1_EL1), @@ -2036,12 +2033,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* AArch64 ID registers */ /* CRm=4 */ - { SYS_DESC(SYS_ID_AA64PFR0_EL1), - .access = access_id_reg, - .get_user = get_id_reg, - .set_user = set_id_reg, - .reset = read_sanitised_id_aa64pfr0_el1, - .val = GENMASK(63, 0), }, + _ID_SANITISED_W(ID_AA64PFR0_EL1, set_id_reg, read_sanitised_id_aa64pfr0_el1), ID_SANITISED(ID_AA64PFR1_EL1), ID_UNALLOCATED(4,2), ID_UNALLOCATED(4,3), @@ -2051,12 +2043,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_UNALLOCATED(4,7), /* CRm=5 */ - { SYS_DESC(SYS_ID_AA64DFR0_EL1), - .access = access_id_reg, - .get_user = get_id_reg, - .set_user = set_id_aa64dfr0_el1, - .reset = read_sanitised_id_aa64dfr0_el1, - .val = GENMASK(63, 0), }, + _ID_SANITISED_W(ID_AA64DFR0_EL1, set_id_aa64dfr0_el1, read_sanitised_id_aa64dfr0_el1), ID_SANITISED(ID_AA64DFR1_EL1), ID_UNALLOCATED(5,2), ID_UNALLOCATED(5,3),