From patchwork Mon Aug 7 16:41:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13344600 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74ADAC00528 for ; Mon, 7 Aug 2023 16:54:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=AoF4rb6JJ0HvhlmQSMydJa6fVKA8tM1WDxORJSZaKpA=; b=g/fwK8Bne6zNfS o6f1sA5LdNeyOLwMzlx7NAgkcGH1dXU8fZiVVCPdwZOFRudT43stU5KE8ZOx5bfs09DhvlhJrX6yR A8u/x3ZGZv7UeoLPliNPZ/fCtiTPfEOYvQ+bZfpf7miodGUW5BOIF0heLIqjVl6SLnz5wJLAT+4RY Frr/o8HpGBiZlC5e6FMerC/qWcNABUFnYzNXn10nYH+vOGPKCUR0CIoJEloiQiT5s8RKx6tFHF4Og 2yijdbPPvydddvhpwue0iZjRimcrUu5e1GoIk1W2nWUs3yhMUZ1Fywczy4J9ecV6vI/oGu7TtIEbO 8AZvvJaD69LbYUiHuGqA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qT3UY-000Elc-0C; Mon, 07 Aug 2023 16:54:02 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qT3UV-000EjV-1Y for linux-arm-kernel@lists.infradead.org; Mon, 07 Aug 2023 16:54:00 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D016A61FAB; Mon, 7 Aug 2023 16:53:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 09B96C433C8; Mon, 7 Aug 2023 16:53:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1691427235; bh=ucsnwmWqR4ajtwvJh+GfJymKYMLxktOm7tZoJmtvJZc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=unOQi/58jran/roL4A+62srL5tGAGlU2R3f/ghuG/muZVv2VIArOIjNCp+hIb6mwA G/UC72SBFHKBrZseylm767aw0RKRDqX08NTfYKYJvDdeKnuesQLyNFwj4/uw76UNAX OGHwV8cVQzAzMxJuAVhoE2hvkxWSVyntfhZN6vBu/5uI/xzS5FFILzy+Wr2UlsU5dP +ZUu3Q1Clu4uKCrLQCINhV2brTAPFbXhjMjdAJK7MG2gRDfD/WOdRDXlbZy7LgNl4i m05RoZN+JlB7baKnNYiE7m/j27r4CuEpth8zVwAXxaCZelX13BgDSUeFbhNVWBtiNW PAkUfCukUkCWA== From: Jisheng Zhang To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v2 06/10] net: stmmac: xgmac: support per-channel irq Date: Tue, 8 Aug 2023 00:41:47 +0800 Message-Id: <20230807164151.1130-7-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230807164151.1130-1-jszhang@kernel.org> References: <20230807164151.1130-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230807_095359_603678_F115F870 X-CRM114-Status: GOOD ( 13.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The IP supports per channel interrupt, add support for this usage case. Signed-off-by: Jisheng Zhang --- .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 ++ .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 33 +++++++++++-------- 2 files changed, 22 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index 81cbb13a101d..12e1228ccf2a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -327,6 +327,8 @@ /* DMA Registers */ #define XGMAC_DMA_MODE 0x00003000 +#define XGMAC_INTM GENMASK(13, 12) +#define XGMAC_INTM_MODE1 0x1 #define XGMAC_SWR BIT(0) #define XGMAC_DMA_SYSBUS_MODE 0x00003004 #define XGMAC_WR_OSR_LMT GENMASK(29, 24) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index b5ba4e0cca55..ef25af92d6cc 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -31,6 +31,13 @@ static void dwxgmac2_dma_init(void __iomem *ioaddr, value |= XGMAC_EAME; writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); + + if (dma_cfg->perch_irq_en) { + value = readl(ioaddr + XGMAC_DMA_MODE); + value &= ~XGMAC_INTM; + value |= FIELD_PREP(XGMAC_INTM, XGMAC_INTM_MODE1); + writel(value, ioaddr + XGMAC_DMA_MODE); + } } static void dwxgmac2_dma_init_chan(struct stmmac_priv *priv, @@ -365,20 +372,20 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *priv, } /* TX/RX NORMAL interrupts */ - if (likely(intr_status & XGMAC_NIS)) { - if (likely(intr_status & XGMAC_RI)) { - u64_stats_update_begin(&rx_q->rxq_stats.syncp); - rx_q->rxq_stats.rx_normal_irq_n++; - u64_stats_update_end(&rx_q->rxq_stats.syncp); - ret |= handle_rx; - } - if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) { - u64_stats_update_begin(&tx_q->txq_stats.syncp); - tx_q->txq_stats.tx_normal_irq_n++; - u64_stats_update_end(&tx_q->txq_stats.syncp); - ret |= handle_tx; - } + if (likely(intr_status & XGMAC_RI)) { + u64_stats_update_begin(&rx_q->rxq_stats.syncp); + rx_q->rxq_stats.rx_normal_irq_n++; + u64_stats_update_end(&rx_q->rxq_stats.syncp); + ret |= handle_rx; + } + if (likely(intr_status & XGMAC_TI)) { + u64_stats_update_begin(&tx_q->txq_stats.syncp); + tx_q->txq_stats.tx_normal_irq_n++; + u64_stats_update_end(&tx_q->txq_stats.syncp); + ret |= handle_tx; } + if (unlikely(intr_status & XGMAC_TBU)) + ret |= handle_tx; /* Clear interrupts */ writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan));