diff mbox series

[net-next,v3,03/10] net: stmmac: mdio: enlarge the max XGMAC C22 ADDR to 31

Message ID 20230809165007.1439-4-jszhang@kernel.org (mailing list archive)
State New, archived
Headers show
Series net: stmmac: add new features to xgmac | expand

Commit Message

Jisheng Zhang Aug. 9, 2023, 4:50 p.m. UTC
The IP can support up to 31 xgmac c22 addresses now.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Alexandre TORGUE Aug. 10, 2023, 1:46 p.m. UTC | #1
On 8/9/23 18:50, Jisheng Zhang wrote:
> The IP can support up to 31 xgmac c22 addresses now.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>   drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> index 3db1cb0fd160..e6d8e34fafef 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> @@ -40,7 +40,7 @@
>   #define MII_XGMAC_WRITE			(1 << MII_XGMAC_CMD_SHIFT)
>   #define MII_XGMAC_READ			(3 << MII_XGMAC_CMD_SHIFT)
>   #define MII_XGMAC_BUSY			BIT(22)
> -#define MII_XGMAC_MAX_C22ADDR		3
> +#define MII_XGMAC_MAX_C22ADDR		31
>   #define MII_XGMAC_C22P_MASK		GENMASK(MII_XGMAC_MAX_C22ADDR, 0)
>   #define MII_XGMAC_PA_SHIFT		16
>   #define MII_XGMAC_DA_SHIFT		21

Acked-by: Alexandre TORGUE <alexandre.torgue@foss.st.com>

Regards
Alex
diff mbox series

Patch

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index 3db1cb0fd160..e6d8e34fafef 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -40,7 +40,7 @@ 
 #define MII_XGMAC_WRITE			(1 << MII_XGMAC_CMD_SHIFT)
 #define MII_XGMAC_READ			(3 << MII_XGMAC_CMD_SHIFT)
 #define MII_XGMAC_BUSY			BIT(22)
-#define MII_XGMAC_MAX_C22ADDR		3
+#define MII_XGMAC_MAX_C22ADDR		31
 #define MII_XGMAC_C22P_MASK		GENMASK(MII_XGMAC_MAX_C22ADDR, 0)
 #define MII_XGMAC_PA_SHIFT		16
 #define MII_XGMAC_DA_SHIFT		21