[v5,1/2] perf/imx_ddr: speed up overflow frequency of cycle

Commit Message

Xu Yang Aug. 11, 2023, 1:54 a.m. UTC

For i.MX8MP, we cannot ensure that cycle counter overflow occurs at least
4 times as often as other events. Due to byte counters will count for any
event configured, it will overflow more often. And if byte counters
overflow that related counters would stop since they share the
COUNTER_CNTL. We can speed up cycle counter overflow frequency by setting
counter parameter (CP) field of cycle counter. In this way, we can avoid
stop counting byte counters when interrupt didn't come and the byte
counters can be fetched or updated from each cycle counter overflow
interrupt.

Because we initialize CP filed to shorten counter0 overflow time, the cycle
counter will start couting from a fixed/base value each time. We need to
remove the base from the result too. Therefore, we could get precise result
from cycle counter.

Signed-off-by: Xu Yang <[e-mail]>
Reviewed-by: Frank Li <[e-mail]>

---
Changes in v5:
 - change comments
Changes in v4:
 - change comments bit error
 - add CYCLES_COUNTER_MASK
Changes in v3:
 - modify the comments as suggested from Mark
 - use mask to remove bias value
 - merge two patches to one
Changes in v2:
 - improve if condition
---
 drivers/perf/fsl_imx8_ddr_perf.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

Will Deacon Aug. 16, 2023, 6:25 p.m. UTC | #1

On Fri, 11 Aug 2023 09:54:37 +0800, Xu Yang wrote:
> For i.MX8MP, we cannot ensure that cycle counter overflow occurs at least
> 4 times as often as other events. Due to byte counters will count for any
> event configured, it will overflow more often. And if byte counters
> overflow that related counters would stop since they share the
> COUNTER_CNTL. We can speed up cycle counter overflow frequency by setting
> counter parameter (CP) field of cycle counter. In this way, we can avoid
> stop counting byte counters when interrupt didn't come and the byte
> counters can be fetched or updated from each cycle counter overflow
> interrupt.
> 
> [...]

Applied to will (for-next/perf), thanks!

[1/2] perf/imx_ddr: speed up overflow frequency of cycle
      https://git.kernel.org/will/c/e89ecd836886
[2/2] perf/imx_ddr: don't enable counter0 if none of 4 counters are used
      https://git.kernel.org/will/c/f4e2bd91ddf5

Cheers,

Patch

diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
index 5222ba1e79d0..b022755e6ab9 100644
--- a/drivers/perf/fsl_imx8_ddr_perf.c
+++ b/drivers/perf/fsl_imx8_ddr_perf.c
@@ -28,6 +28,8 @@ 
 #define CNTL_CLEAR_MASK		0xFFFFFFFD
 #define CNTL_OVER_MASK		0xFFFFFFFE
 
+#define CNTL_CP_SHIFT		16
+#define CNTL_CP_MASK		(0xFF << CNTL_CP_SHIFT)
 #define CNTL_CSV_SHIFT		24
 #define CNTL_CSV_MASK		(0xFFU << CNTL_CSV_SHIFT)
 
@@ -35,6 +37,8 @@ 
 #define EVENT_CYCLES_COUNTER	0
 #define NUM_COUNTERS		4
 
+/* For removing bias if cycle counter CNTL.CP is set to 0xf0 */
+#define CYCLES_COUNTER_MASK	0x0FFFFFFF
 #define AXI_MASKING_REVERT	0xffff0000	/* AXI_MASKING(MSB 16bits) + AXI_ID(LSB 16bits) */
 
 #define to_ddr_pmu(p)		container_of(p, struct ddr_pmu, pmu)
@@ -427,6 +431,17 @@  static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
 		writel(0, pmu->base + reg);
 		val = CNTL_EN | CNTL_CLEAR;
 		val |= FIELD_PREP(CNTL_CSV_MASK, config);
+
+		/*
+		 * On i.MX8MP we need to bias the cycle counter to overflow more often.
+		 * We do this by initializing bits [23:16] of the counter value via the
+		 * COUNTER_CTRL Counter Parameter (CP) field.
+		 */
+		if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
+			if (counter == EVENT_CYCLES_COUNTER)
+				val |= FIELD_PREP(CNTL_CP_MASK, 0xf0);
+		}
+
 		writel(val, pmu->base + reg);
 	} else {
 		/* Disable counter */
@@ -466,6 +481,12 @@  static void ddr_perf_event_update(struct perf_event *event)
 	int ret;
 
 	new_raw_count = ddr_perf_read_counter(pmu, counter);
+	/* Remove the bias applied in ddr_perf_counter_enable(). */
+	if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
+		if (counter == EVENT_CYCLES_COUNTER)
+			new_raw_count &= CYCLES_COUNTER_MASK;
+	}
+
 	local64_add(new_raw_count, &event->count);
 
 	/*