@@ -219,6 +219,8 @@ struct stmmac_priv {
int hwts_tx_en;
bool tx_path_in_lpi_mode;
bool tso;
+ bool tx_q_coe_lmt;
+ u32 tx_q_with_coe;
int sph;
int sph_cap;
u32 sarc_type;
@@ -4409,6 +4409,17 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
WARN_ON(tx_q->tx_skbuff[first_entry]);
csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
+ /* Some DWMAC IPs support tx coe only for a few initial tx queues,
+ * starting from tx queue 0. So checksum offloading for those queues
+ * that don't support tx coe needs to fallback to software checksum
+ * calculation.
+ */
+ if (csum_insertion && priv->tx_q_coe_lmt &&
+ queue >= priv->tx_q_with_coe) {
+ if (unlikely(skb_checksum_help(skb)))
+ goto dma_map_err;
+ csum_insertion = !csum_insertion;
+ }
if (likely(priv->extend_desc))
desc = (struct dma_desc *)(tx_q->dma_etx + entry);
@@ -7386,6 +7397,14 @@ int stmmac_dvr_probe(struct device *device,
dev_info(priv->device, "SPH feature enabled\n");
}
+ if (priv->plat->tx_coe &&
+ priv->plat->tx_queues_with_coe < priv->plat->tx_queues_to_use) {
+ priv->tx_q_coe_lmt = true;
+ priv->tx_q_with_coe = priv->plat->tx_queues_with_coe;
+ dev_info(priv->device, "TX COE limited to %u tx queues\n",
+ priv->tx_q_with_coe);
+ }
+
/* Ideally our host DMA address width is the same as for the
* device. However, it may differ and then we have to use our
* host DMA width for allocation and the device DMA width for
@@ -225,6 +225,10 @@ static int stmmac_mtl_setup(struct platform_device *pdev,
&plat->tx_queues_to_use))
plat->tx_queues_to_use = 1;
+ if (of_property_read_u32(tx_node, "snps,tx-queues-with-coe",
+ &plat->tx_queues_with_coe))
+ plat->tx_queues_with_coe = plat->tx_queues_to_use;
+
if (of_property_read_bool(tx_node, "snps,tx-sched-wrr"))
plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
else if (of_property_read_bool(tx_node, "snps,tx-sched-wfq"))
@@ -252,6 +252,7 @@ struct plat_stmmacenet_data {
u32 host_dma_width;
u32 rx_queues_to_use;
u32 tx_queues_to_use;
+ u32 tx_queues_with_coe;
u8 rx_sched_algorithm;
u8 tx_sched_algorithm;
struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
Add sw fallback of tx checksum calculation for those tx queues that don't support tx checksum offloading. Because, some DWMAC IPs support tx checksum offloading only for a few initial tx queues, starting from tx queue 0. Signed-off-by: Rohan G Thomas <rohan.g.thomas@intel.com> --- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 19 +++++++++++++++++++ .../ethernet/stmicro/stmmac/stmmac_platform.c | 4 ++++ include/linux/stmmac.h | 1 + 4 files changed, 26 insertions(+)