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Sun, 13 Aug 2023 15:13:24 GMT Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Sun, 13 Aug 2023 08:13:19 -0700 From: Mao Jinlong To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin , Andy Gross , "Bjorn Andersson" , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Mao Jinlong , , , , , , Tingwei Zhang , Yuanfang Zhang , "Tao Zhang" , Hao Zhang Subject: [PATCH v2 2/3] dt-bindings: arm: Adds CoreSight CSR hardware definitions Date: Sun, 13 Aug 2023 23:12:52 +0800 Message-ID: <20230813151253.38128-3-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230813151253.38128-1-quic_jinlmao@quicinc.com> References: <20230813151253.38128-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: UPM36FqdDuj5fw0XqnoHYq5CYw51cSST X-Proofpoint-ORIG-GUID: UPM36FqdDuj5fw0XqnoHYq5CYw51cSST X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-13_15,2023-08-10_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 clxscore=1015 malwarescore=0 impostorscore=0 spamscore=0 bulkscore=0 mlxlogscore=738 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308130143 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230813_081341_957152_ED64C7A9 X-CRM114-Status: GOOD ( 23.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds new coresight-csr.yaml file describing the bindings required to define csr in the device trees. Signed-off-by: Mao Jinlong --- .../bindings/arm/qcom,coresight-csr.yaml | 130 ++++++++++++++++++ MAINTAINERS | 2 +- include/dt-bindings/arm/coresight-csr-dt.h | 12 ++ 3 files changed, 143 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml create mode 100644 include/dt-bindings/arm/coresight-csr-dt.h diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml new file mode 100644 index 000000000000..de4baa335fdb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CoreSight Slave Register - CSR + +description: | + CoreSight Slave Register block hosts miscellaneous configuration registers. + Those configuration registers can be used to control, various coresight + configurations. + +maintainers: + - Mao Jinlong + - Hao Zhang + +properties: + $nodename: + pattern: "^csr(@[0-9a-f]+)$" + compatible: + items: + - const: qcom,coresight-csr + + reg: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + # size cells and address cells required if assoc_device node present. + "#size-cells": + const: 0 + + "#address-cells": + const: 1 + +patternProperties: + '^assoc_device@([0-9]+)$': + type: object + description: + A assocated device child node which describes the required configs + between this CSR and another hardware device. This device may be ETR or + TPDM device. + + properties: + reg: + maxItems: 1 + + arm,cs-dev-assoc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + defines a phandle reference to an associated CoreSight trace device. + When the associated trace device is enabled, then the respective CSR + will be enabled. If the associated device has not been registered + then the node name will be stored as the assocated name for later + resolution. + + qcom,cs-dev-type: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Device type of the Assocated device. Types are in coresight-csr-dt.h. + + qcom,csr-bytecntr-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The ETR irqctrl register offset. If the assocated device is ETR + device and there are more than one ETR devices, this property need + to be added. + + interrupts: + minItems: 1 + + interrupt-names: + minItems: 1 + + required: + - reg + - qcom,cs-dev-type + - qcom,cs-dev-assoc + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + # minimum CSR definition. + - | + csr@10001000 { + compatible = "qcom,coresight-csr"; + reg = <0 0x10001000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + # Assocated with ETR device + - | + #include + #include + + csr@10001000 { + compatible = "qcom,coresight-csr"; + reg = <0 0x10001000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + #address-cells = <1>; + #size-cells = <0>; + assoc_device@0 { + reg = <0>; + qcom,cs-dev-type = ; + qcom,cs-dev-assoc = <&tmc_etr>; + qcom,csr-bytecntr-offset = <0x6c>; + interrupts = ; + interrupt-names = "byte-cntr-irq"; + }; + }; +... + diff --git a/MAINTAINERS b/MAINTAINERS index d516295978a4..3ed81a8fd1d0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2042,7 +2042,7 @@ F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml F: Documentation/devicetree/bindings/arm/qcom,coresight-*.yaml F: Documentation/trace/coresight/* F: drivers/hwtracing/coresight/* -F: include/dt-bindings/arm/coresight-cti-dt.h +F: include/dt-bindings/arm/coresight-*.h F: include/linux/coresight* F: samples/coresight/* F: tools/perf/arch/arm/util/auxtrace.c diff --git a/include/dt-bindings/arm/coresight-csr-dt.h b/include/dt-bindings/arm/coresight-csr-dt.h new file mode 100644 index 000000000000..804b9bbeb2bd --- /dev/null +++ b/include/dt-bindings/arm/coresight-csr-dt.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * This header provides constants for the defined device + * types on CoreSight CSR. + */ + +#ifndef _DT_BINDINGS_ARM_CORESIGHT_CSR_DT_H +#define _DT_BINDINGS_ARM_CORESIGHT_CSR_DT_H + +#define CSR_ASSOC_DEV_ETR 1 + +#endif /*_DT_BINDINGS_ARM_CORESIGHT_CSR_DT_H */