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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zX9AaEbi6FSPFIYiiAdLu8TGwK66MYIKC2XIWb6IsBVU2M1th34aPaWQgCil2cwKRZchWVLDXm4kVy0vTm21YJvE5Y4838AU4vknF7yqhcbnwrC/gz8G8XoabQnjTZv5QO84H0yIIo/Tzv0Tj2JoLBWrLCVO+v2oU6DoMCl/Dypmr2YYJKb4RVCXDqx9dkbS5PjeG+VOoe50kfa584pPTgmjm8E2fFwoi/AfI9n/NRIRxhSwdqZGFzWDLx5mmgU5qBCoES+C08yyS05GTbTw4XM0h4zhurM7r2HYpGSf1m+nVBAXR3MbE4CotaXtoj7Trdzag7AkfhnkB8wruc4RG32XZcav9pXHDxVkBdqhWJFTzYrDe8WzocZfMfeyVIDY99OA4jWbVXX3nE9nAo04G+2jR3BXokNBD7XKgGt0BzMUTQsjeZ6py/529TmVBwVwujTJHfx4MoaYEU45K5sFL0bZPpgSFh/uNSFNC+JtgITrEkGI92L1pYBX2cMcxoBrTcgfkZIb0WeEtOD7FCIp2qosfZBoymtKyguIDoDMqoTTP49ZAc978udQijukuvb3z8RGlWCRuSi1n9HYD+MGJZSxs5hy7/wQDnQTzjuxffIoKrMJH7p6T6U+vzRoArHPI27ov2Ivjlug+OpyxqhGhCEZJlD58SbZkuqXPqEyV/mb8V3vIq98MMLWy9XuQVGGEL4ipsgydFEBelfvMBh4YohUQK/HTj4wQGGf/uKJsbjaSkXMQRG/94W699C6I/9XbQyD02I4xq5K5b/1If6CYVdJrIWwaPws34k5oQvpxrN+1MXlwdrz734GlxpzRWhWT8FJQPItnFDduBWUupuyzs8Ruk+Iu+CTa9uGzvnHTyjnkLlYGH5Z9cbb7LPlfQB01tfJEeoWtRVQdrs+UzqgpyWrPJtcGwsajmPX0uBcfEWdo2B96MndrZnXEepxEjXULB5F9HryNzv2aS1ZPo/NOVWRVyNIb7ftHH7dEAjqntuEJNWt4fB6oj0Kbj4B1yceQmuxNHKE8XyHIHcFLVcRtHdPxRWUk3T6m50c33LAay4jIzWlyVhnyccL9M9wtEGuKHhtbrjhNC5dL+J2kdMRYkC4WYhwrmlzd/6uk2DZDeL2he5y2FH2Teqylnr7tgrOXTKNqmskaoS+7qtV3NpHq4IYE9PLf6SkeqGv/8yef6/SXolSG7nhsDJsp4+PR5xOtvhy9XMXLYuLEp+KEw4BBj/h+Z9jcl7ydLJfrBphNWIyb6PEkRhL1sSnhA1HIvF3QjZwAH4yXEG3R7cOgTfNE6yJzzna6X+zlRu8DA+x+bnAF+rem7PrNPVFD9Rhd8ihZshXBY1Lr0UnVRsPdkqOj0HDur7Gl7rCair1BiVo4Mn+dP+vXiZa171kVAflckbMvkA8CfNt9k2LHWv3TH85+KvSsa/lhuk+YU4Nb3ehaImg6T6E8lzC8/dEBYrec0xeeipG03hAn/heliHsLva6H6V8AUjuAXWaS+ThMIg5X7KkDVu+fnj64zaAzUJ5k7lLmiXZ2SDRbfjPIhktbJyEVHgOEXFDIoXNYITzjhGBgj/0XgLETbD9o1cpxkSFQJr/ttEmQ5XdLid6G5b+QKOmVQ== X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: e8008f31-30d7-4896-521c-08db9d59e8f2 X-MS-Exchange-CrossTenant-AuthSource: DM5PR0102MB3590.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2023 06:36:09.0101 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 17nOJTGo2MM76xYjDtnGmHbMPdo0KczfCh2DqtT9c+3EUGHhmLwcGqLAO3kMbVetUVclzVYmjCwtOhLwPl9LJTa/n6HRht1QuN1Wur3CAZoJMAYRgwmU6YxhyTYI12Gf X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR01MB6117 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230814_233614_275989_4AFABA38 X-CRM114-Status: GOOD ( 14.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org ARM Coresight PMU architecture specification [1] defines PMEVTYPER and PMEVFILT* registers as optional in Chapter 2.1. Moreover, implementers may choose to use PMIMPDEF* registers (offset: 0xD80-> 0xDFF) to filter the events. Add support for those by adding implementation specific filter callback function. [1] https://developer.arm.com/documentation/ihi0091/latest Signed-off-by: Ilkka Koskinen Reviewed-by: Besar Wicaksono Reviewed-by: Suzuki K Poulose --- drivers/perf/arm_cspmu/arm_cspmu.c | 12 ++++++++---- drivers/perf/arm_cspmu/arm_cspmu.h | 3 +++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c index 6387cbad7a7d..94f6856ec786 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -116,6 +116,9 @@ static unsigned long arm_cspmu_cpuhp_state; static DEFINE_MUTEX(arm_cspmu_lock); +static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, + struct hw_perf_event *hwc, u32 filter); + static struct acpi_apmt_node *arm_cspmu_apmt_node(struct device *dev) { return *(struct acpi_apmt_node **)dev_get_platdata(dev); @@ -450,6 +453,7 @@ static int arm_cspmu_init_impl_ops(struct arm_cspmu *cspmu) CHECK_DEFAULT_IMPL_OPS(impl_ops, event_type); CHECK_DEFAULT_IMPL_OPS(impl_ops, event_filter); CHECK_DEFAULT_IMPL_OPS(impl_ops, event_attr_is_visible); + CHECK_DEFAULT_IMPL_OPS(impl_ops, set_ev_filter); return 0; } @@ -811,9 +815,9 @@ static inline void arm_cspmu_set_event(struct arm_cspmu *cspmu, writel(hwc->config, cspmu->base0 + offset); } -static inline void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, - struct hw_perf_event *hwc, - u32 filter) +static void arm_cspmu_set_ev_filter(struct arm_cspmu *cspmu, + struct hw_perf_event *hwc, + u32 filter) { u32 offset = PMEVFILTR + (4 * hwc->idx); @@ -845,7 +849,7 @@ static void arm_cspmu_start(struct perf_event *event, int pmu_flags) arm_cspmu_set_cc_filter(cspmu, filter); } else { arm_cspmu_set_event(cspmu, hwc); - arm_cspmu_set_ev_filter(cspmu, hwc, filter); + cspmu->impl.ops.set_ev_filter(cspmu, hwc, filter); } hwc->state = 0; diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h b/drivers/perf/arm_cspmu/arm_cspmu.h index e5c6dff2ce7f..274ca3d10578 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.h +++ b/drivers/perf/arm_cspmu/arm_cspmu.h @@ -104,6 +104,9 @@ struct arm_cspmu_impl_ops { u32 (*event_type)(const struct perf_event *event); /* Decode filter value from configs */ u32 (*event_filter)(const struct perf_event *event); + /* Set event filter */ + void (*set_ev_filter)(struct arm_cspmu *cspmu, + struct hw_perf_event *hwc, u32 filter); /* Hide/show unsupported events */ umode_t (*event_attr_is_visible)(struct kobject *kobj, struct attribute *attr, int unused);