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Wed, 16 Aug 2023 03:42:52 -0700 (PDT) Received: from hsinyi-z840.tpe.corp.google.com ([2401:fa00:1:10:40cf:3807:f8c8:2d76]) by smtp.gmail.com with ESMTPSA id kx14-20020a170902f94e00b001b8a3dd5a4asm2899270plb.283.2023.08.16.03.42.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Aug 2023 03:42:52 -0700 (PDT) From: Hsin-Yi Wang To: Tudor Ambarus , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Bjorn Andersson Cc: Pratyush Yadav , Michael Walle , "Miquel Raynal )" , "Richard Weinberger )" , "Vignesh Raghavendra )" , Rob Herring , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, cros-qcom-dts-watchers@chromium.org, Andy Gross , Konrad Dybcio Subject: [PATCH v2,1/2] mtd: spi-nor: giga: gd25lq64c: Disable quad mode according to bus width Date: Wed, 16 Aug 2023 18:38:32 +0800 Message-ID: <20230816104245.2676965-1-hsinyi@chromium.org> X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230816_034255_637038_95C32279 X-CRM114-Status: GOOD ( 17.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org gd25lq64c has Quad Enable Requirement flag parsed as BFPT_DWORD15_QER_SR2_BIT1_BUGGY in BFPT, even if spi-{rx/tx}-bus-width set as non QUAD, eg. 0, 1, 2... Thus quad_enable will not be NULL and quad enable (QE) bit will be set to 1 by default. According to datasheet[1], if QE bit is enabled, WP pin will become IO pin and the system can't use write protection feature, and it's also not recommended to set QE bit to 1[1]. Add a post_bfpt fixup that reads spi-rx-bus-width to remove quad_enable if the width is set to below QUAD mode. [1] https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00012-GD25LQ64C-Rev3.4.pdf page 13 Signed-off-by: Hsin-Yi Wang --- drivers/mtd/spi-nor/gigadevice.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c index d57ddaf1525b3..8ea89e1858f9b 100644 --- a/drivers/mtd/spi-nor/gigadevice.c +++ b/drivers/mtd/spi-nor/gigadevice.c @@ -33,6 +33,31 @@ static const struct spi_nor_fixups gd25q256_fixups = { .post_bfpt = gd25q256_post_bfpt, }; +static int +gd25lq64c_post_bfpt(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt) +{ + struct device_node *np = spi_nor_get_flash_node(nor); + u32 value; + + /* + * Even if spi-{tx,rx}-bus-width is set to DUAL mode, due to the QER + * flag parsed from BFPT is BFPT_DWORD15_QER_SR2_BIT1_BUGGY, so the + * quad_enable will be set and QE bit set to 1. + */ + if (!of_property_read_u32(np, "spi-rx-bus-width", &value)) { + if (value <= 2) + nor->params->quad_enable = NULL; + } + + return 0; +} + +static struct spi_nor_fixups gd25lq64c_fixups = { + .post_bfpt = gd25lq64c_post_bfpt, +}; + static const struct flash_info gigadevice_nor_parts[] = { { "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) @@ -53,7 +78,8 @@ static const struct flash_info gigadevice_nor_parts[] = { { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | - SPI_NOR_QUAD_READ) }, + SPI_NOR_QUAD_READ) + .fixups = &gd25lq64c_fixups }, { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |