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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6HBOUurHAEaSd+TmBTfPaCyDF2NFRRXC4dYu8pMwjeImNdAN7Mr6r4jizFL3OOJgKM7Nky/poVzUwt2oBPAES4BDCFaNYk9GWPvHR27E5PcLB+QJOlQ233pIxlBQ6W0oxUGgjY4s8ddZLov/GswXDYQ4rZJ3zh+Zbqgb1p1p6ZXlFMrJ1mBMySxUJAsc1oY+Dt/hSPQNe6zM4tY/a7lh1MKPZNawzEWpCNOM0H8FbgJAN82IGg1bRN5u5lB8LHld+7aI7QDJvTvWprptLEhbjntF3ueBySH0B41Z+W+WMMT9yK8mR+xaDangAbk64MDu9GHvkyx8YlXlLNED5QDO9dS2YML7s7bGYxc+MLgpbDCXfdUz9RTTXSV3w5Ud7yEytK4SNVYOR3Y5DC1qKlo875uD/7eVsxOo0NveY+I10CNr0DDnDWRu8tQ68ewl4vQRj4VTe195E2soxx+TJ5j0RmGwm5frjYeMYhJQfF1dZUjKH5F8BKxiX4JH44es4DuHUdQEEPxgyM9ct5iMUGqoSWfsLIQHXcf98oHmelDXx0feeBLZPF56IGvlSge1JbPW3wV1kmLsmONFvRCpHhfxxDaPE8cLTKaMhbU8Q3ymCKJIVdzFpaiP0STzjZic/THwmjcqiU+vNwBgO3p/w60DoBzinwlNrUThtbspFWvTTx6CLfzp5mmkA4rwnlNCilaWud4vnSvTzcv5UzWRS9Re4/oUC/X175bbiWdYJcpIAK8SpzJtMfPnB9j9vJas4IiN2IIVGkXLx6mdd5fDAoXP2Wf+FFxz/bEcHd1nfCVk9UfoxhNVRtzbpPxLnNddQ+X4XChZrLecy5XTOMQgOQae7P6q1sj1ZLQuk+gqWKgyZyWLKSnJA3ifrhv1KrQsJHFsq1BahHl+IcUl2/JZBukcpm17V/ETtl+Hw7d6w8Rfv4B02rJc9HU5Vhl1zYaaRkRYOcaeeENvex/yt/kmftXLcY+yUjqpHYg87LVDd6yno8ZA1hetyLlUSocjX6l5ZUyA4LBEdCbukVnnW5xbXqYWoOQYVo1V5IxUQxM+zKj+hqfbg6H6++7BTMj+T08DQlHP4xoi06CXtlq/1Zn0yyt2XrLtTzhe7M8HWs3uQdPV9H5UDXpj5jATWG1EC5MCcWGHgqtUSbLq01I1QzO1VG07seXCOpjlM/6ye114+naiRyfaASWtcn32cQqdn/ksRcFLhIFFctV2biuB8u6QDScVTqFFRvpe1gVSgy6XXdN+yozciFtF+0XqKY7Xv/eDZr8qdkyMFcQf+jiMiMpA9p1iUIKq96YzUkKSVdoxrEEXaM8kQgpDGGDnAZrx+Baw6deJbdx2WxDZhczIUXqfAajLJ3guRRHZzqHNmYDOOlzv2A2YNWSp+6nkfUcs24v0cUyJpq0KMPLBZD625Gcm7QW+onFeXYyIE3N83Lm4eTY+rwspQyvq/cPEu5vxeJwM0bDR24RnQBerChcJlZpFEdRW0pUiHlWrTa3xW8QyLUSjvScbnAsLissCJAOFk124xAqbeseBrZzfBBFZ0rlZX3Vy6Ez+f1kbeFHZQMiyPIlgXDvkiBdBu6dtTLA7Babt5XzCZQVNvKVDTMGb9tvkJT/ut+xo/3Gf23aUm9uBe0cudPI= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5ca9ed8a-fa8c-4ba0-cc25-08db9ee7b1d8 X-MS-Exchange-CrossTenant-AuthSource: DM8PR01MB6824.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Aug 2023 06:03:36.3086 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zPaLAaoNP19Z5J5R3Kk8uyDOvEMTuZMaJtUR5vo8herX72zbMh64tUJM+HFp6WY8lFLkmi4dRJxq8trRJy3dpf7UwLKPtwsLBv9CrLQv5kQWRs8tL/jgKVWUJX83Mr17 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR01MB6592 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230816_230345_079685_8355F2BD X-CRM114-Status: GOOD ( 12.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org As per FEAT_ECV, when HCR_EL2.{E2H, TGE} == {1, 1}, Enhanced Counter Virtualization functionality is disabled and CNTPOFF_EL2 value is treated as zero. On VHE host, E2H and TGE are set, hence it is required to adjust CVAL by incrementing it by CNTPOFF_EL2 after guest exit to avoid false physical timer interrupts and also decrement/restore CVAL before the guest entry. Signed-off-by: Ganapatrao Kulkarni --- arch/arm64/kvm/arch_timer.c | 32 ++++++++++++++++++++++++++++++++ arch/arm64/kvm/hyp/vhe/switch.c | 13 +++++++++++++ include/kvm/arm_arch_timer.h | 1 + 3 files changed, 46 insertions(+) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 98b0e8ac02ae..be609b12827d 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -955,6 +955,38 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu) kvm_timer_blocking(vcpu); } +static void ptimer_cval_adjust(struct arch_timer_context *ctx, bool inc) +{ + struct arch_timer_cpu *timer = vcpu_timer(ctx->vcpu); + unsigned long flags; + u64 cval, offset; + + if (!timer->enabled || !ctx->loaded) + return; + + local_irq_save(flags); + offset = timer_get_offset(ctx); + if (offset) { + cval = read_sysreg_el0(SYS_CNTP_CVAL); + if (inc) + cval += offset; + else + cval -= offset; + write_sysreg_el0(cval, SYS_CNTP_CVAL); + isb(); + } + local_irq_restore(flags); +} + +void kvm_ptimer_cval_adjust(struct kvm_vcpu *vcpu, bool inc) +{ + struct timer_map map; + + get_timer_map(vcpu, &map); + if (map.direct_ptimer) + ptimer_cval_adjust(map.direct_ptimer, inc); +} + void kvm_timer_sync_nested(struct kvm_vcpu *vcpu) { /* diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c index 561cb53e19ce..0cdcefc1351d 100644 --- a/arch/arm64/kvm/hyp/vhe/switch.c +++ b/arch/arm64/kvm/hyp/vhe/switch.c @@ -100,6 +100,10 @@ static void __activate_traps(struct kvm_vcpu *vcpu) hcr |= vhcr_el2; } + /* Decrement/Restore CVAL by CNTPOFF. */ + if (has_cntpoff()) + kvm_ptimer_cval_adjust(vcpu, false); + ___activate_traps(vcpu, hcr); val = read_sysreg(cpacr_el1); @@ -141,6 +145,15 @@ static void __deactivate_traps(struct kvm_vcpu *vcpu) ___deactivate_traps(vcpu); + /* + * For VHE Host, HCR_EL2.{E2H, TGE} is {1, 1}, hence FEAT_ECV + * is disabled and CNTPOFF_EL2 value is treated as zero. + * Need to increment CVAL for non-zero CNTPOFF to avoid + * false PTIMER interrupt. + */ + if (has_cntpoff()) + kvm_ptimer_cval_adjust(vcpu, true); + write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); /* diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index ea77a569a907..3ce6f02a0d9b 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -117,6 +117,7 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu); void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu); void kvm_timer_init_vhe(void); +void kvm_ptimer_cval_adjust(struct kvm_vcpu *vcpu, bool inc); #define vcpu_timer(v) (&(v)->arch.timer_cpu) #define vcpu_get_timer(v,t) (&vcpu_timer(v)->timers[(t)])