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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uddQ3fjdnviYYr+dPUXpT80xc3sPMXYjQPa21lRs3QpMY4vE7eQ2c9TgXOcr4Siqhn+/Zg/n/sbvFNF4gHMaeHYMWJnwJG3wPNSS3yJ5w3mwGSsl7DPGtkThWyGQVbHTFGqwG29WPNmw9Va+N5mqgAyW6dKQvCghvGwkDb5iRVIm9uY52sQ/U0Mtq7irEteJOHRhrnH4kJCFTs67eQQpep4xlJqqRjYJ+401WSpViXlfEPZqkHMMDxEmQLfEbyJyS1LIsQkgNsM6DCVGzW/p5+4UOLhmD4OE28okVd6JzIpzRpGQCf6fA887UEaxC4XeaJIn7nvUWQ89ojFXwsxpLFs/pjwv1n/aBcaMLUBK3ydGkz/NLCIcY8PRwnTHCUMdZENxbKko1TIX5xBG+thknKkBjayPQ6PBFGnvMdK2Sy0twu65WmQg5D/9EZ3eC5L5ORGZFcjW2N/LBF68Mp1zDBMUFPcPHqvjsJC/PjyS7USgkGzWMhUR2FYHn5JMXPgZEfbPwBz93p2gccLx673JBuym0U+/H+WFIIxMwKIXD8QS/pUK0nbugRu7DIMS3IdVt0UqQKq+QeR+JZ4bdi5BE2BLLhvd3Auuops5MOBNW+MHYA0aBvAwN/0t5AfIrIuxuDOt5jsGJS+Hw/UKlrRuYAm7ZzKgJdN357oDyr8rLs2nEO26kvGo8ZpWV5528P9pVwP1yC2C1qdILu6IzhQ0WU6UKJ/kfQqPLkMbavFXoZTEFDP/ELFlorDttbLE3kIDrd8Fon9dg0ZTvJJtz0az6CFFMrxtKLAUz67hE3y1clFV+IUE5VutNfST+dG5e2MIEuCC+GzIuJv9kOo7uoYLmh2RU/DRXf1oK2KnG7gYx8pkfUqNtfbXKrSpYECbF2TH9oa5ejCQ1Xuw7pTq6rVAycU1Jqib/BdyKbaJMUUyAl6iz94TMuVni11FI+62Ev89sJeWqhroSq+/A2RYZo9mpqQpfvizxRO/Uk40zpmZmT5S/V3shjrbz1Qb6xUc5q63LtUBYzfQeeKNtZR5R1Y7+dCHOKXhQbp1NVr5ldAL+mR9vT4zaQh5uj8SM1VRvqOWWCo/dr30IWtKCJ9/6u1s//S683AdBb4LChS4vyJIUt2NgVmrOtrU2g3DSnlZD1LfvARY7zHfzvas1PCUk+YFKkkM0czDds6kko0S3gOzthadFytzDFNoF35Kg1rceMEciB5GG0657DHmEF+J0BQ/HVqd2ZrJ3UYmjyikvBiZSp+jSm1sffqX/W3Mt0ZmSVUKHi4WkaVE2063aTtztJXsEf9Cu50NCNFDDP2RNZeEVFMrlIg72Ed6GKH2K35Mnx7YGcakTfNYcQnjDtiTYxGLZAMPE8Xo9dlHU3p7MnjphbhU6cZ4QaBdSsDt5QQ8uHkMjJwwJc6eYZBlzBPklM6ITEfZllv54ZgvlM9KKCRQMOAP3+Vs/+8/1Z/KCzkbldJr0kio1qQNEhgvkTzCK55sx/nYnFAq+y6ZamOKT9GqPPgwApXKooGM5gC9GNqBLY0OpLktdafdzFGbNFlXWipzjYzuWKRURg3qqYk5AOpZbjCITixjwp+ot+LvFaPGBf/y X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9129bc78-5c2e-4e29-cf08-08dba2ed9b61 X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 08:56:00.4235 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: l0eCWL/nLgY8BZCJwzDe1XT9907BjajHJn/R7BFGFjDEK6Wzzz74MvdbMPEWJEQUXr+NXT4M3JTkFJdHlL4rhQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS5PR04MB9970 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230822_015605_594773_15D25DD4 X-CRM114-Status: GOOD ( 16.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel. Reviewed-by: Rob Herring Signed-off-by: Liu Ying --- v10->v14: * No change. v9->v10: * Add Rob's R-b tag. v8->v9: * Reference 'interrupts-extended' schema instead of 'interrupts' to require an additional interrupt(r_rtram_stall) because the reference manual does mention it, though the driver doesn't get/use it for now. Reference 'interrupt-names' schema to define the two interrupt names - 'dpr_wrap' and 'r_rtram_stall'. * Drop Rob's R-b tag, as review is needed. v4->v8: * No change. v3->v4: * Improve compatible property by using enum instead of oneOf+const. (Rob) * Add Rob's R-b tag. v2->v3: * No change. v1->v2: * Use new dt binding way to add clocks in the example. .../display/imx/fsl,imx8qxp-dprc.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml new file mode 100644 index 000000000000..bd94254c1288 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel + +maintainers: + - Liu Ying + +description: | + The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which + fetches display data before the display pipeline needs the data to drive + pixels in the active display region. This data is transformed, or resolved, + from a variety of tiled buffer formats into linear format, if needed. + The DPR works with a double bank memory structure. This memory structure is + implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to + as A and B. Each bank is either 4 or 8 lines high depending on the source + frame buffer format. + +properties: + compatible: + enum: + - fsl,imx8qxp-dpr-channel + - fsl,imx8qm-dpr-channel + + reg: + maxItems: 1 + + interrupts-extended: + items: + - description: DPR wrap interrupt + - description: | + 'r_rtram_stall' interrupt which indicates relevant i.MX8qm/qxp + Prefetch Resolve Gasket(PRG) or PRGs are forcing an underflow + condition in the RTRAM. + + interrupt-names: + items: + - const: dpr_wrap + - const: r_rtram_stall + + clocks: + items: + - description: apb clock + - description: b clock + - description: rtram clock + + clock-names: + items: + - const: apb + - const: b + - const: rtram + + fsl,sc-resource: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The SCU resource ID associated with this DPRC instance. + + fsl,prgs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandle which points to PRG or PRGs associated with + this DPRC instance. + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts-extended + - interrupt-names + - clocks + - clock-names + - fsl,sc-resource + - fsl,prgs + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + dpr-channel@56100000 { + compatible = "fsl,imx8qxp-dpr-channel"; + reg = <0x56100000 0x10000>; + interrupts-extended = <&gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <&dc0_irqsteer 324>; + interrupt-names = "dpr_wrap", "r_rtram_stall"; + clocks = <&dc0_dpr1_lpcg IMX_LPCG_CLK_4>, + <&dc0_dpr1_lpcg IMX_LPCG_CLK_5>, + <&dc0_rtram1_lpcg IMX_LPCG_CLK_0>; + clock-names = "apb", "b", "rtram"; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg4>, <&dc0_prg5>; + power-domains = <&pd IMX_SC_R_DC_0>; + };