| Message ID | 20230825093528.1637-3-shameerali.kolothum.thodi@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm64: Implement SW/HW combined dirty log | expand |
Hi Shameer, On Fri, Aug 25, 2023 at 10:35:22AM +0100, Shameer Kolothum wrote: > KVM_PGTABLE_WALK_HW_DBM - Indicates page table walk is for HW DBM > related updates. > > No functional changes here. Only apply any HW DBM bit updates to last > level only. These will be used by a future commit where we will add > support for HW DBM. > > Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> > --- > arch/arm64/include/asm/kvm_pgtable.h | 3 +++ > arch/arm64/kvm/hyp/pgtable.c | 10 ++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > index d3e354bb8351..3f96bdd2086f 100644 > --- a/arch/arm64/include/asm/kvm_pgtable.h > +++ b/arch/arm64/include/asm/kvm_pgtable.h > @@ -219,6 +219,8 @@ typedef bool (*kvm_pgtable_force_pte_cb_t)(u64 addr, u64 end, > * @KVM_PGTABLE_WALK_SKIP_CMO: Visit and update table entries > * without Cache maintenance > * operations required. > + * @KVM_PGTABLE_WALK_HW_DBM: Indicates that the attribute update is > + * HW DBM related. > */ > enum kvm_pgtable_walk_flags { > KVM_PGTABLE_WALK_LEAF = BIT(0), > @@ -228,6 +230,7 @@ enum kvm_pgtable_walk_flags { > KVM_PGTABLE_WALK_HANDLE_FAULT = BIT(4), > KVM_PGTABLE_WALK_SKIP_BBM_TLBI = BIT(5), > KVM_PGTABLE_WALK_SKIP_CMO = BIT(6), > + KVM_PGTABLE_WALK_HW_DBM = BIT(7), > }; Rather than making this DBM specific, call it KVM_PGTABLE_WALK_FORCE_PTE and get rid of stage2_map_data::force_pte. Then it becomes immediately obvious what this flag implies.
> -----Original Message----- > From: Oliver Upton [mailto:oliver.upton@linux.dev] > Sent: 15 September 2023 23:06 > To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com> > Cc: kvmarm@lists.linux.dev; kvm@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; maz@kernel.org; will@kernel.org; > catalin.marinas@arm.com; james.morse@arm.com; > suzuki.poulose@arm.com; yuzenghui <yuzenghui@huawei.com>; zhukeqian > <zhukeqian1@huawei.com>; Jonathan Cameron > <jonathan.cameron@huawei.com>; Linuxarm <linuxarm@huawei.com> > Subject: Re: [RFC PATCH v2 2/8] KVM: arm64: Add > KVM_PGTABLE_WALK_HW_DBM for HW DBM support > > Hi Shameer, > > On Fri, Aug 25, 2023 at 10:35:22AM +0100, Shameer Kolothum wrote: > > KVM_PGTABLE_WALK_HW_DBM - Indicates page table walk is for HW > DBM > > related updates. > > > > No functional changes here. Only apply any HW DBM bit updates to last > > level only. These will be used by a future commit where we will add > > support for HW DBM. > > > > Signed-off-by: Shameer Kolothum > <shameerali.kolothum.thodi@huawei.com> > > --- > > arch/arm64/include/asm/kvm_pgtable.h | 3 +++ > > arch/arm64/kvm/hyp/pgtable.c | 10 ++++++++++ > > 2 files changed, 13 insertions(+) > > > > diff --git a/arch/arm64/include/asm/kvm_pgtable.h > b/arch/arm64/include/asm/kvm_pgtable.h > > index d3e354bb8351..3f96bdd2086f 100644 > > --- a/arch/arm64/include/asm/kvm_pgtable.h > > +++ b/arch/arm64/include/asm/kvm_pgtable.h > > @@ -219,6 +219,8 @@ typedef bool (*kvm_pgtable_force_pte_cb_t)(u64 > addr, u64 end, > > * @KVM_PGTABLE_WALK_SKIP_CMO: Visit and update table > entries > > * without Cache maintenance > > * operations required. > > + * @KVM_PGTABLE_WALK_HW_DBM: Indicates that the attribute > update is > > + * HW DBM related. > > */ > > enum kvm_pgtable_walk_flags { > > KVM_PGTABLE_WALK_LEAF = BIT(0), > > @@ -228,6 +230,7 @@ enum kvm_pgtable_walk_flags { > > KVM_PGTABLE_WALK_HANDLE_FAULT = BIT(4), > > KVM_PGTABLE_WALK_SKIP_BBM_TLBI = BIT(5), > > KVM_PGTABLE_WALK_SKIP_CMO = BIT(6), > > + KVM_PGTABLE_WALK_HW_DBM = BIT(7), > > }; > > Rather than making this DBM specific, call it > KVM_PGTABLE_WALK_FORCE_PTE > and get rid of stage2_map_data::force_pte. Then it becomes immediately > obvious what this flag implies. Ok. Will change accordingly. Thanks, Shameer
diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h index d3e354bb8351..3f96bdd2086f 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -219,6 +219,8 @@ typedef bool (*kvm_pgtable_force_pte_cb_t)(u64 addr, u64 end, * @KVM_PGTABLE_WALK_SKIP_CMO: Visit and update table entries * without Cache maintenance * operations required. + * @KVM_PGTABLE_WALK_HW_DBM: Indicates that the attribute update is + * HW DBM related. */ enum kvm_pgtable_walk_flags { KVM_PGTABLE_WALK_LEAF = BIT(0), @@ -228,6 +230,7 @@ enum kvm_pgtable_walk_flags { KVM_PGTABLE_WALK_HANDLE_FAULT = BIT(4), KVM_PGTABLE_WALK_SKIP_BBM_TLBI = BIT(5), KVM_PGTABLE_WALK_SKIP_CMO = BIT(6), + KVM_PGTABLE_WALK_HW_DBM = BIT(7), }; struct kvm_pgtable_visit_ctx { diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index f155b8c9e98c..1e65b8c97059 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -67,6 +67,11 @@ struct kvm_pgtable_walk_data { const u64 end; }; +static bool kvm_pgtable_walk_hw_dbm(const struct kvm_pgtable_visit_ctx *ctx) +{ + return ctx->flags & KVM_PGTABLE_WALK_HW_DBM; +} + static bool kvm_pgtable_walk_skip_bbm_tlbi(const struct kvm_pgtable_visit_ctx *ctx) { return unlikely(ctx->flags & KVM_PGTABLE_WALK_SKIP_BBM_TLBI); @@ -1164,6 +1169,11 @@ static int stage2_attr_walker(const struct kvm_pgtable_visit_ctx *ctx, if (!kvm_pte_valid(ctx->old)) return -EAGAIN; + /* Only apply HW DBM for last level */ + if (kvm_pgtable_walk_hw_dbm(ctx) && + ctx->level != (KVM_PGTABLE_MAX_LEVELS - 1)) + return 0; + data->level = ctx->level; data->pte = pte; pte &= ~data->attr_clr;
KVM_PGTABLE_WALK_HW_DBM - Indicates page table walk is for HW DBM related updates. No functional changes here. Only apply any HW DBM bit updates to last level only. These will be used by a future commit where we will add support for HW DBM. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> --- arch/arm64/include/asm/kvm_pgtable.h | 3 +++ arch/arm64/kvm/hyp/pgtable.c | 10 ++++++++++ 2 files changed, 13 insertions(+)