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Tue, 29 Aug 2023 14:41:57 -0700 (PDT) Received: from U4.lan ([2001:9e8:b963:7410:84d2:f616:9527:dd98]) by smtp.gmail.com with ESMTPSA id f15-20020aa7d84f000000b0052228721f84sm6113428eds.77.2023.08.29.14.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 14:41:57 -0700 (PDT) From: Alex Bee To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alex Bee Subject: [PATCH v2 2/4] ARM: dts: rockchip: Add CPU resets for RK3128 Date: Tue, 29 Aug 2023 23:40:05 +0200 Message-ID: <20230829214004.314932-6-knaerzche@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829214004.314932-2-knaerzche@gmail.com> References: <20230829214004.314932-2-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230829_144201_818570_540C2DC6 X-CRM114-Status: GOOD ( 12.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In order to support bring-up of the non-boot cores, this patch adds the reset controls for the cpu cores. They are required/will be used by the Rockchip platsmp driver. Signed-off-by: Alex Bee --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 3a0856973795..2778049003a1 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -34,6 +34,7 @@ cpu0: cpu@f00 { reg = <0xf00>; clock-latency = <40000>; clocks = <&cru ARMCLK>; + resets = <&cru SRST_CORE0>; operating-points = < /* KHz uV */ 816000 1000000 @@ -45,18 +46,21 @@ cpu1: cpu@f01 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf01>; + resets = <&cru SRST_CORE1>; }; cpu2: cpu@f02 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf02>; + resets = <&cru SRST_CORE2>; }; cpu3: cpu@f03 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf03>; + resets = <&cru SRST_CORE3>; }; };