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Wed, 30 Aug 2023 04:07:29 -0500 From: Thippeswamy Havalige To: , , , , , CC: , , , , , Thippeswamy Havalige , Krzysztof Kozlowski Subject: [PATCH v7 2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Date: Wed, 30 Aug 2023 14:37:06 +0530 Message-ID: <20230830090707.278136-3-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230830090707.278136-1-thippeswamy.havalige@amd.com> References: <20230830090707.278136-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD4:EE_|BY5PR12MB4869:EE_ X-MS-Office365-Filtering-Correlation-Id: c25de3ad-9991-4363-59a1-08dba9388ca0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NHLZkve401ADdQ4Q7YOLGJBsfoNXT4ZfXCHrdEQjwOXgV6q7EQyX0XYj2c556B/olqRyFItpkwHb7PEmAw2pkKb1994Ub/JXGJfEjnmTT+lDwsk03jvtJToys3jbxYwiiMp+1jtUDJXy/D/4wf6tXqgZJQeqqpRMD5Hp8lU+sWMlw1d/c88YEPXKZJtzorxWrA8J+3QUwA1YriOUEsTw56x+GXe6rY2Gb0U9hl/WqlloXxoi04H4jAgd4qahCgN4Dwn2gszHvx7Yuz9IF6tk7NIIigr5RxLlfNT7PhXA2Pg9c5egB0A4450HrqSHhOhcABftIsbEjBDdAo5+uXd/hvg5LgJtyKY0ENXMXkWZnbcdp2Wln4A50UFVNVWTiUY8eegK2I649gWgTJe//LMv2t2QxjSO39xdzuWNhqWBuctYBp/9r3JQBIU76Db4inj8kRVUFz9y1FhYFBNklbc5BbdExYSR3TauPcwY5aJIThzomNK8e+7v3lj7V4h685nAFFd6WpNLTJM52HT/D0HViOryF68PiuZDV7jKF+QrCOi0oa1MQwQ6deJhcYXJcvP6rwyPVLAyv/53FWbUCVshkEA4sEsThuqlcHBM9uW6GnUS4oE2PaGxqOtEo7sgqMapTZ6KTCYWU5PcTtcmnL6N/pEF7D6pJC5uflEUAGA5ldGoy3k9VKMK61Tl77n9x16AX1izFKdiSqHo+idUBxIah3qSBN2TWXDI6sNKVOANvHJwmIlOXJQWJqq4MvNZ7tPUNFxd1cSgHjwFRz1QOYMD9Q61i7wMq6LnG5Smu8SsHac7zb8V58gAHTiZTZcGhA2Q X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(346002)(39860400002)(376002)(451199024)(186009)(1800799009)(82310400011)(36840700001)(46966006)(40470700004)(6666004)(4326008)(82740400003)(86362001)(40480700001)(36756003)(36860700001)(356005)(47076005)(478600001)(426003)(110136005)(70586007)(26005)(336012)(966005)(2906002)(81166007)(40460700003)(70206006)(8676002)(5660300002)(8936002)(316002)(44832011)(1076003)(2616005)(7416002)(54906003)(41300700001)(36900700001)(2101003);DIR:OUT;SFP:1101; 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Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- changes in v7: - None changes in v6: - None change in v5: - Modified uppercase case hex value to lower case. change in v4: - Removed unnecessary space. changes in v3: - Fixed compatible string issue. - Modified ranges property description to maxItems. - Modified address-cell property of interrupt-controller child node. changes in v2: - None --- .../devicetree/bindings/pci/xlnx,xdma-host.yaml | 114 +++++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml new file mode 100644 index 0000000..0aa00b8 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx XDMA PL PCIe Root Port Bridge + +maintainers: + - Thippeswamy Havalige + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: xlnx,xdma-host-3.00 + + reg: + maxItems: 1 + + ranges: + maxItems: 2 + + interrupts: + items: + - description: interrupt asserted when miscellaneous interrupt is received. + - description: msi0 interrupt asserted when an MSI is received. + - description: msi1 interrupt asserted when an MSI is received. + + interrupt-names: + items: + - const: misc + - const: msi0 + - const: msi1 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + interrupt-map: + maxItems: 4 + + "#interrupt-cells": + const: 1 + + interrupt-controller: + description: identifies the node as an interrupt controller + type: object + properties: + interrupt-controller: true + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + required: + - interrupt-controller + - "#address-cells" + - "#interrupt-cells" + + additionalProperties: false + +required: + - compatible + - reg + - ranges + - interrupts + - interrupt-map + - interrupt-map-mask + - "#interrupt-cells" + - interrupt-controller + +unevaluatedProperties: false + +examples: + + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie@a0000000 { + compatible = "xlnx,xdma-host-3.00"; + reg = <0x0 0xa0000000 0x0 0x10000000>; + ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>, + <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = , , + ; + interrupt-names = "misc", "msi0", "msi1"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + pcie_intc_0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + };