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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: j+WZyY5WJ8UU0aH9gXN8h29DHzzGgj4kXGdgALmsHenswCtkqDdD3hBumHyPdve1sn34yOMAAGCMPKKLQ7FOhzbdjoj7wFhsajpXo8K9mY8GlxgkICCr07E5qJgr7ov4XnEvEAYeDh79SqTQRB0eyFn964O0aa/5IeHg/zstsgn6eAeImw7AqQYjI/0YChC7EZKWYyrnk0lD0M+CFddcD7HyucCvuEVrTsFXcmCkTshEO4i7nmYxENv7vPheLNGnIqpEJH9K9Lrrj2tRkbulbk+5OqTEb7kgJ+Zw3guCWGei5K5Z9fiq4a/R3YMd2uI27/SrsCY2Iqjk0FRnD98oDIi/A94FvdmzC3kfMOUv/2B3t5XKQCrj1B6oT4Dc0V+7VRVjZyXmA9CyVuf3c1l4b6um3BupARAzpwVl91FUj5tIYBOYEtLoc/uySrcrOXTMQo3Dr98oz9GbQESscpNdUjzlxKkSh+F5H66IMLY7nmJAqgmrqUFjC8W+ZOUorA5EPROJSn7aT9NuZw77yMk4EOhBLYkgtY21Soueb2JzInS6eORXeFTeVQl2Q+w357K14bbMNxSxu7u6HixL24+XTbJMvVzmdxop0FJJhK5fn0tsI7bkOfhqMjY8Ph/maGHRmlHgCXh+nTG7rTqT8Ldk8TjZoKF0XB4gMNgwU/QCTC9xZ9YB4vK1flmJ5c3VKAlZJFybywqqBz8vbjasmRExFZMZ1uRVICaq/fWwoT9XMbpOOYyBCOKSZCJCCM7Rux3el7AJBixE1CW1JQZvKDP52cePzpiH+pUXcBXNu3wFSggx94mtgxJtdF0mE8bWz9d1aRqMKf0zv6TRcBtFqjVzqN/oQPasX/siJQEoeVoBqcgTxcEN1bpY6el7Dh7AN/uCPh30KIctzLJRdaxouGf1dQv2ykq7w5YM7SJhFxtFoWoR6obre4RFkLG8OVeh1F29IQD4LxoNFDBSF/WPnEuI4mHMVwC76Ne66pMOnnwGViGskuWaO3mCRbZXXO7oYielkQpgs7NTikFnWi7WbdFeKPE7PWzML9Zqcgxh6Iq/lQcdByATJkXpKesA4awYSuWq72AjfhD898eALVxN5sNA7o0Ip804M6qUraGx0wJlrNRBHzWjlfvYckDK3V66dIF6iXwFzICjQjUhNrfh2SQrgFDKrJOURZp+twm2bTQhDoNp34X8DgK7ZYnoZcmFz4CRQ0K8Hr9XNEaJrhETtBbZ7oCVPcRl5jWpYUGcPIOb9zV7hK7rWFd7x+wgXA84MNy5NGiajDQX1TXfzdsL4gEBWfuLe2RyA52t2OLT7jmEbyAs+0dEnjZOtdzzQCqkAD5ZVn8pX+nd86Y955BBexeHdPUgyLs+F/3OMLKBWGK2h9nHFPkbDMqHG1wLtzCrpkslG0XDpfbjqQkcAMKTd2TX6GKEeZbGOSt9O+hognhVkIFf7/Zg6t+qvLHnyL2s3EqIEIrDmitjqrO+OU6ESjGQSQyWMIn2D5t4/PzPExMLiBAAxwA1/jACkQlFrBfeMpIukz1k1l3zpdGJbdmbokjgo/WF2ZFCAFNZVwY6FAZVS7ARgcToX85SrV7OQM5m7x5zLDY9ygAqeKythAn8m1uyUpgz0mvcqpbWB+A/Y5jaoLs= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 89ca01ec-441b-498d-7346-08dbad3c0e8a X-MS-Exchange-CrossTenant-AuthSource: SJ2PR01MB8101.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 11:42:45.8548 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /Pmhp/k8R2WV4hh5Q6YUSe5h7KFi8nFLnoqCu5cOZEdPexVmwDi5LfJnp6GJ8ME69C3xOwEwamn3R+bXNhroSOoOsxIrnWrpTb+DX0UMEx3z2xYypKfoHLyj2TrRdPYL X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR01MB8008 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230904_044303_540190_E9FC8C0D X-CRM114-Status: GOOD ( 14.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org As per FEAT_ECV, when HCR_EL2.{E2H, TGE} == {1, 1}, Enhanced Counter Virtualization functionality is disabled and CNTPOFF_EL2 value is treated as zero. On VHE host, E2H and TGE are set, hence it is required to save Guest's CVAL to memory and increment it by CNTPOFF_EL2 at guest exit to avoid false physical timer interrupts and also restore back the CVAL with saved value before the guest entry. Signed-off-by: Ganapatrao Kulkarni Reported-by: Ganapatrao Kulkarni Signed-off-by: Marc Zyngier Tested-by: Ganapatrao Kulkarni --- arch/arm64/kvm/arch_timer.c | 60 ++++++++++++++++++++++++++++++--- arch/arm64/kvm/hyp/vhe/switch.c | 13 +++++++ include/kvm/arm_arch_timer.h | 1 + 3 files changed, 69 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 98b0e8ac02ae..9fe3fa6ed98a 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -514,6 +514,59 @@ static void set_cntpoff(u64 cntpoff) write_sysreg_s(cntpoff, SYS_CNTPOFF_EL2); } +static void ptimer_cval_save(struct arch_timer_context *ctx, u64 offset) +{ + unsigned long flags; + u64 cval; + + local_irq_save(flags); + cval = read_sysreg_el0(SYS_CNTP_CVAL); + timer_set_cval(ctx, cval); + cval += offset; + write_sysreg_el0(cval, SYS_CNTP_CVAL); + isb(); + local_irq_restore(flags); +} + +static void ptimer_cval_restore(struct arch_timer_context *ctx, u64 offset) +{ + unsigned long flags; + u64 cval; + + local_irq_save(flags); + cval = timer_get_cval(ctx); + write_sysreg_el0(cval, SYS_CNTP_CVAL); + isb(); + local_irq_restore(flags); +} + +void kvm_ptimer_cval_save_restore(struct kvm_vcpu *vcpu, bool save) +{ + struct timer_map map; + struct arch_timer_cpu *timer; + struct arch_timer_context *ctxp; + u64 offset; + + get_timer_map(vcpu, &map); + ctxp = map.direct_ptimer; + + if (unlikely(ctxp == NULL)) + return; + + offset = timer_get_offset(ctxp); + if (!offset) + return; + + timer = vcpu_timer(ctxp->vcpu); + if (!timer->enabled || !ctxp->loaded) + return; + + if (save) + ptimer_cval_save(ctxp, offset); + else + ptimer_cval_restore(ctxp, offset); +} + static void timer_save_state(struct arch_timer_context *ctx) { struct arch_timer_cpu *timer = vcpu_timer(ctx->vcpu); @@ -562,9 +615,7 @@ static void timer_save_state(struct arch_timer_context *ctx) timer_set_ctl(ctx, read_sysreg_el0(SYS_CNTP_CTL)); cval = read_sysreg_el0(SYS_CNTP_CVAL); - if (!has_cntpoff()) - cval -= timer_get_offset(ctx); - + cval -= timer_get_offset(ctx); timer_set_cval(ctx, cval); /* Disable the timer */ @@ -650,8 +701,7 @@ static void timer_restore_state(struct arch_timer_context *ctx) cval = timer_get_cval(ctx); offset = timer_get_offset(ctx); set_cntpoff(offset); - if (!has_cntpoff()) - cval += offset; + cval += offset; write_sysreg_el0(cval, SYS_CNTP_CVAL); isb(); write_sysreg_el0(timer_get_ctl(ctx), SYS_CNTP_CTL); diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c index 561cb53e19ce..097fcaf7b208 100644 --- a/arch/arm64/kvm/hyp/vhe/switch.c +++ b/arch/arm64/kvm/hyp/vhe/switch.c @@ -100,6 +100,10 @@ static void __activate_traps(struct kvm_vcpu *vcpu) hcr |= vhcr_el2; } + /* Restore CVAL */ + if (has_cntpoff()) + kvm_ptimer_cval_save_restore(vcpu, false); + ___activate_traps(vcpu, hcr); val = read_sysreg(cpacr_el1); @@ -141,6 +145,15 @@ static void __deactivate_traps(struct kvm_vcpu *vcpu) ___deactivate_traps(vcpu); + /* + * For VHE Host, HCR_EL2.{E2H, TGE} is {1, 1}, FEAT_ECV + * is disabled and CNTPOFF_EL2 value is treated as zero. + * Hence, need to save guest written CVAL in memory and + * increment PTIMER's CVAL by CNTPOFF to avoid false interrupt. + */ + if (has_cntpoff()) + kvm_ptimer_cval_save_restore(vcpu, true); + write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); /* diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index ea77a569a907..ce3f4d9e7dd4 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -117,6 +117,7 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu); void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu); void kvm_timer_init_vhe(void); +void kvm_ptimer_cval_save_restore(struct kvm_vcpu *vcpu, bool save); #define vcpu_timer(v) (&(v)->arch.timer_cpu) #define vcpu_get_timer(v,t) (&vcpu_timer(v)->timers[(t)])