From patchwork Tue Sep 5 10:47:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 13374424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E690C83F33 for ; Tue, 5 Sep 2023 10:48:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jMe331K6daOOJd+96RPU8unvMOd7MebtuGmyYBLvHs8=; b=vabx+GStMa2TKZ LC4lj/z+kxgeWb7YgqGt/M9i9Dtdun9dt6OeUhUuW3YiVjPhy9MexNSXF83mp+waLQoLQHm01gVgS C+viUOTM7n1QSMX6cwBTCqWY6G5GOkrEK+gkqebreNZuW+cQWoKFuYkM98WKiWpeUnvRI1V6jR3fs qm6x0c27vJpozloSl1fxJu679ZVgQj4Dtff+V51YfUG0Wa1iniuTDXmq2zkoTOhqvf9SRD+KFJuhc vhvw8zc9zkm+dCqEsew4QndvATkB2r5CPGEGs73cduHfocCnTXoBhrjVN8FerSI51L/Lb5suAxb2c p8z7LH6eBtWufduaZ77w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qdTap-005qxc-2F; Tue, 05 Sep 2023 10:47:35 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qdTan-005qwq-0H for linux-arm-kernel@lists.infradead.org; Tue, 05 Sep 2023 10:47:34 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9D2796068A; Tue, 5 Sep 2023 10:47:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9F996C433C8; Tue, 5 Sep 2023 10:47:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1693910852; bh=rwu/ICLddZviRmw2ibPmYNuYJYieVb9gj5s0F4BZk2g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PrektR0OvmkeZ5I62+XN2ZIEywqRUsADhv8DRXcKFRY3TThydbyXNpJNtEQTDhLR6 7cTVGugCfDArcKjy3J27sspy6ipEILeBNKTHDJBBXyl+vfB2ET+qnVdZgfXJKjtj5d rr5/JKUI2zujSKXAXAGp+sYXMqZT78CuCGItBfb2S5i8U+XT9OpAv3Tz7GvKvy9+0f wFEVU+/eX7FWDAMZE+0pmvcMm4NRagPiMcyilymVkbgUjm24ithPCw+zh9ppw59ZrR gcpUbwIDD55dqVJJ7vonbA9mDBrQZsz3VR1N8ba1JPe6Jm1vsk/Sa0ZNUsHzxXBEDI 2E7i3zzRy1y4A== From: Lorenzo Pieralisi To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Mark Rutland , Robin Murphy , Rob Herring , Fang Xiang , Marc Zyngier Subject: [PATCH 1/2] dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property Date: Tue, 5 Sep 2023 12:47:20 +0200 Message-Id: <20230905104721.52199-2-lpieralisi@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905104721.52199-1-lpieralisi@kernel.org> References: <20230905104721.52199-1-lpieralisi@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230905_034733_164875_B8FEDF6F X-CRM114-Status: GOOD ( 11.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The GIC v3 specifications allow redistributors and ITSes interconnect ports used to access memory to be wired up in a way that makes the respective initiators/memory observers non-coherent. Add the standard dma-noncoherent property to the GICv3 bindings to allow firmware to describe the redistributors/ITSes components and interconnect ports behaviour in system designs where the redistributors and ITSes are not coherent with the CPU. Signed-off-by: Lorenzo Pieralisi Cc: Rob Herring --- .../bindings/interrupt-controller/arm,gic-v3.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml index 39e64c7f6360..0a81ae4519a6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -106,6 +106,10 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 maximum: 4096 + dma-noncoherent: + description: | + Present if the GIC redistributors are not cache coherent with the CPU. + msi-controller: description: Only present if the Message Based Interrupt functionality is @@ -193,6 +197,10 @@ patternProperties: compatible: const: arm,gic-v3-its + dma-noncoherent: + description: | + Present if the GIC ITS is not cache coherent with the CPU. + msi-controller: true "#msi-cells":