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Thu, 7 Sep 2023 11:15:00 -0700 From: To: , , , , , CC: , , , , , , , , , , , Subject: [PATCH v1 2/2] KVM: arm64: allow the VM to select DEVICE_* and NORMAL_NC for IO memory Date: Thu, 7 Sep 2023 11:14:59 -0700 Message-ID: <20230907181459.18145-3-ankita@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230907181459.18145-1-ankita@nvidia.com> References: <20230907181459.18145-1-ankita@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC5:EE_|DM4PR12MB6469:EE_ X-MS-Office365-Filtering-Correlation-Id: 567b9141-f874-4537-7f10-08dbafce5f1e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4mnDT81U7AQITPoNCJSezBIzT2LzZ9NvGswTaOTfb6GXMPMpsLP5uKFlR/Aa/oZZ38GmlYPayg3KgRD6DZGZUmznJI6v1RoOcMIqVkqK0UScwNx77s7uLypKMjBxPPBQytdVrC9zPxmEceGcW+EZy6zFFgWHiojtZdstp3oIwu74flGzddJORKY/KK7Fse5MyMWc0McW1B266zNy3tSbBOB93cODj89avZfIXDvHqPp1kM6MdU5Ht4TRWmySL0Fm1zGbYhMO6r2Nsx7/vzzdNHdcFyg0kSsoIPMerA5oAwvjgMwFoC3+sqhZaQ8jOE5vruhmRrhesv5zAAmUJwNomnBxe5QPlBu8ac11gPRo8kY5UNu/aYf9sVOSufkH309CnRlRozvg92WUtT/QEZodvLQNJpjJ5DKivdP//I1gq/OJsyhuY+cPRHE40xxCKLj4LqYvR9SwKin8D8C4MGGHxLoXUM5fYTw9++8AhVt6MeJQzvafaev9TunHuFl/Dzwho0tDB6h+ZMJiIuDm402AVUGBc2QepiuUceNtyFQNbAO8XVLfLFVG/9B23vuTQGFeULYlXufdyvjNFmS1/p5YJFv4XhomzkGDBButXe4uAA2OBJUYvzF/x54NgTTG3dAYIA3sk+sFm2z6vwOFlOYVf23BHdu2wDKBsvJpbYS+nH2X/JOybGPBAAion3P3S1SaCWHANob0SnzIkcVkr3+FRPrxfjDoUpZx9xo/sygVYTR9VVskmZbfSBM2jCuWnZqn X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(346002)(136003)(39860400002)(451199024)(1800799009)(186009)(82310400011)(46966006)(36840700001)(40470700004)(54906003)(316002)(2616005)(82740400003)(1076003)(36860700001)(86362001)(110136005)(70586007)(2876002)(70206006)(2906002)(41300700001)(8676002)(4326008)(8936002)(47076005)(5660300002)(19627235002)(336012)(426003)(478600001)(40480700001)(7636003)(26005)(356005)(7696005)(40460700003)(83380400001)(36756003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2023 18:15:09.5608 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 567b9141-f874-4537-7f10-08dbafce5f1e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6469 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230907_111515_934750_E497FA3E X-CRM114-Status: GOOD ( 16.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Ankit Agrawal Linux allows device drivers to map IO memory on a per-page basis using "write combining" or WC. This is often done using pgprot_writecombing(). The driver knows which pages can support WC access and the proper programming model to generate this IO. Generally the use case is to boost performance by using write combining to generate larger PCIe MemWr TLPs. Allow VMs to select DEVICE_* or NORMAL_NC on a page by page basis for all IO memory. This puts the VM in charge of the memory attributes, and removes the KVM override to DEVICE_nGnRE. Ultimately this makes pgprot_writecombing() work correctly in VMs and allows drivers like mlx5 to fully operate their HW. After some discussions with ARM and CPU architects we reached the conclusion there was no need for KVM to prevent the VM from selecting between DEVICE_* and NORMAL_NC for IO memory in VMs. There was a fear that NORMAL_NC could result in uncontained failures, but upon deeper analysis it turns out there are already possible cases for uncontained failures with DEVICE types too. Ultimately the platform must be implemented in a way that ensures that all DEVICE_* and NORMAL_NC accesses have no uncontained failures. Fortunately real platforms do tend to implement this. This patch makes the VM's memory attributes behave as follows:  S1           |   S2          |  Result  NORMAL-WB    |  NORMAL-NC    |  NORMAL-NC  NORMAL-WT    |  NORMAL-NC    |  NORMAL-NC  NORMAL-NC    |  NORMAL-NC    |  NORMAL-NC  DEVICE |  NORMAL-NC    |  DEVICE See section D8.5.5 of DDI0487_I_a_a-profile_architecture_reference_manual.pdf for details. Signed-off-by: Ankit Agrawal Reviewed-by: Catalin Marinas --- arch/arm64/include/asm/memory.h | 2 ++ arch/arm64/kvm/hyp/pgtable.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index fde4186cc387..c247e5f29d5a 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -147,6 +147,7 @@ * Memory types for Stage-2 translation */ #define MT_S2_NORMAL 0xf +#define MT_S2_NORMAL_NC 0x5 #define MT_S2_DEVICE_nGnRE 0x1 /* @@ -154,6 +155,7 @@ * Stage-2 enforces Normal-WB and Device-nGnRE */ #define MT_S2_FWB_NORMAL 6 +#define MT_S2_FWB_NORMAL_NC 5 #define MT_S2_FWB_DEVICE_nGnRE 1 #ifdef CONFIG_ARM64_4K_PAGES diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index ccd291b6893d..a80949002191 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -696,7 +696,7 @@ static int stage2_set_prot_attr(struct kvm_pgtable *pgt, enum kvm_pgtable_prot p kvm_pte_t *ptep) { bool device = prot & KVM_PGTABLE_PROT_DEVICE; - kvm_pte_t attr = device ? KVM_S2_MEMATTR(pgt, DEVICE_nGnRE) : + kvm_pte_t attr = device ? KVM_S2_MEMATTR(pgt, NORMAL_NC) : KVM_S2_MEMATTR(pgt, NORMAL); u32 sh = KVM_PTE_LEAF_ATTR_LO_S2_SH_IS;