From patchwork Wed Sep 20 08:01:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver Upton X-Patchwork-Id: 13392255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51FFACE79AD for ; Wed, 20 Sep 2023 08:02:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=AHpB1XHceH9OX65S1NmyT33dsrX8KWYspG2AvhVffN0=; b=H6saJ769gpkQvF znu0BknlrjYYTpCzmuVCRjbWsZmsIRGAxCOvawZfh4Qxh0tQ6FLhZ5JKeFI0o/lEO2/ii4QBcr8pQ ouGOkWmCIlrMf0P5IDniB/TaVIFgn7WcsUXm6nkMdnSWBFnvSdrwjBWurkBPGzS5gfwJpz7yiTFd4 EgergMnLxEmvAachayqPkLanCw6XUGNayoArfWOGDoTwcfKvzHl/IEZvGHNTGaWru63APP2GmWjXx /3tKn04ifVXjQErz/oprm+f+w7xpJAjGUM1g1mmVsieLps94xscjLPOLgT8XhB+/a/XD2KN41inHc h8lGwJ6BJJuPCiBBC1HA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qis9r-002DWE-0i; Wed, 20 Sep 2023 08:02:03 +0000 Received: from out-224.mta1.migadu.com ([95.215.58.224]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qis9o-002DTH-0z for linux-arm-kernel@lists.infradead.org; Wed, 20 Sep 2023 08:02:01 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1695196909; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xfbh8qQL9QW5BcJKxEDXewQuyfv4M5lak2q1jy6348Q=; b=kJfWlYzUpeP9zIU/DMOihsHo4wNb5lISvzWIPxEGTfLtXeW7QzzHIIFQUt9VdXyBJ1qfNl XiaSonGNvCmM14etc2Y/yw2NIdjgpfkvUQetSAj2KPbk3CxgvpQSN8SiJ0Wq53/yyOAWAy WmgKUWt8goAWcxpo1wvmmhksbPK/EN8= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, Marc Zyngier , James Morse , Suzuki K Poulose , Zenghui Yu , Will Deacon , Catalin Marinas , linux-arm-kernel@lists.infradead.org, Gavin Shan , Oliver Upton Subject: [PATCH 1/2] arm64: tlbflush: Rename MAX_TLBI_OPS Date: Wed, 20 Sep 2023 08:01:32 +0000 Message-ID: <20230920080133.944717-2-oliver.upton@linux.dev> In-Reply-To: <20230920080133.944717-1-oliver.upton@linux.dev> References: <20230920080133.944717-1-oliver.upton@linux.dev> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230920_010200_491294_1986F598 X-CRM114-Status: GOOD ( 10.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Perhaps unsurprisingly, I-cache invalidations suffer from performance issues similar to TLB invalidations on certain systems. TLB and I-cache maintenance all result in DVM on the mesh, which is where the real bottleneck lies. Rename the heuristic to point the finger at DVM, such that it may be reused for limiting I-cache invalidations. Signed-off-by: Oliver Upton Reviewed-by: Gavin Shan Tested-by: Gavin Shan Acked-by: Will Deacon --- arch/arm64/include/asm/tlbflush.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index b149cf9f91bc..3431d37e5054 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -333,7 +333,7 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) * This is meant to avoid soft lock-ups on large TLB flushing ranges and not * necessarily a performance improvement. */ -#define MAX_TLBI_OPS PTRS_PER_PTE +#define MAX_DVM_OPS PTRS_PER_PTE /* * __flush_tlb_range_op - Perform TLBI operation upon a range @@ -413,12 +413,12 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, /* * When not uses TLB range ops, we can handle up to - * (MAX_TLBI_OPS - 1) pages; + * (MAX_DVM_OPS - 1) pages; * When uses TLB range ops, we can handle up to * (MAX_TLBI_RANGE_PAGES - 1) pages. */ if ((!system_supports_tlb_range() && - (end - start) >= (MAX_TLBI_OPS * stride)) || + (end - start) >= (MAX_DVM_OPS * stride)) || pages >= MAX_TLBI_RANGE_PAGES) { flush_tlb_mm(vma->vm_mm); return; @@ -451,7 +451,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end { unsigned long addr; - if ((end - start) > (MAX_TLBI_OPS * PAGE_SIZE)) { + if ((end - start) > (MAX_DVM_OPS * PAGE_SIZE)) { flush_tlb_all(); return; }