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Wed, 20 Sep 2023 12:28:53 -0700 (PDT) Received: from localhost ([85.140.6.11]) by smtp.gmail.com with ESMTPSA id eo25-20020a056512481900b00500b3157ec8sm2790111lfb.163.2023.09.20.12.28.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:28:53 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 10/18] EDAC/synopsys: Get corrected bit position Date: Wed, 20 Sep 2023 22:26:55 +0300 Message-ID: <20230920192806.29960-11-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920192806.29960-1-fancer.lancer@gmail.com> References: <20230920192806.29960-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230920_122855_683985_D7AD1594 X-CRM114-Status: GOOD ( 19.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since the DQ-bus width is now available in the driver it can be utilized to calculate the exact bit-position corrected by the ECC engine for any Synopsys memory controller setup. A corrected error syndrome is exposed by the ECCSTAT.corrected_bit_num field. A particular erroneous bit position is described in the lookup table [1] which also contains a dependency between the field value and the DQ-bus widths. The syndrome values table basically represents a standard lookup table for the Hamming (64,8)/(32,7)/(16,6) codes (the error-correcting bits placed at the power-of-two positions) except that the zero value means error in the ecc[0] bit. So using the offsets from that table introduce a new inline method snps_get_bitpos() which would provide the actual CE bit-position. The method will be called if a corrected error is detected. [1] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p.426-427 Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index e10778cead63..e08cb30b7a7d 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -301,6 +302,7 @@ struct snps_ddrc_info { * @col: Column number. * @bank: Bank number. * @bankgrp: Bank group number. + * @syndrome: Error syndrome. * @bitpos: Bit position. * @data: Data causing the error. */ @@ -309,6 +311,7 @@ struct snps_ecc_error_info { u32 col; u32 bank; u32 bankgrp; + u32 syndrome; u32 bitpos; u32 data; }; @@ -359,6 +362,27 @@ struct snps_edac_priv { #endif }; +/** + * snps_get_bitpos - Get DQ-bus corrected bit position. + * @syndrome: Error syndrome. + * @dq_width: Controller DQ-bus width. + * + * Return: actual corrected DQ-bus bit position starting from 0. + */ +static inline u32 snps_get_bitpos(u32 syndrome, enum snps_dq_width dq_width) +{ + /* ecc[0] bit */ + if (syndrome == 0) + return BITS_PER_BYTE << dq_width; + + /* ecc[1:x] bit */ + if (is_power_of_2(syndrome)) + return (BITS_PER_BYTE << dq_width) + ilog2(syndrome) + 1; + + /* data[0:y] bit */ + return syndrome - ilog2(syndrome) - 2; +} + /** * snps_get_error_info - Get the current ECC error info. * @priv: DDR memory controller private instance data. @@ -379,7 +403,7 @@ static int snps_get_error_info(struct snps_edac_priv *priv) if (!regval) return 1; - p->ceinfo.bitpos = FIELD_GET(ECC_STAT_BITNUM_MASK, regval); + p->ceinfo.syndrome = FIELD_GET(ECC_STAT_BITNUM_MASK, regval); regval = readl(base + ECC_ERRCNT_OFST); p->ce_cnt = FIELD_GET(ECC_ERRCNT_CECNT_MASK, regval); @@ -387,6 +411,8 @@ static int snps_get_error_info(struct snps_edac_priv *priv) if (!p->ce_cnt) goto ue_err; + p->ceinfo.bitpos = snps_get_bitpos(p->ceinfo.syndrome, priv->info.dq_width); + regval = readl(base + ECC_CEADDR0_OFST); p->ceinfo.row = FIELD_GET(ECC_CEADDR0_ROW_MASK, regval);