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Wed, 20 Sep 2023 12:28:26 -0700 (PDT) Received: from localhost ([178.176.85.138]) by smtp.gmail.com with ESMTPSA id d19-20020a2eb053000000b002b9ec22d9fasm1105300ljl.29.2023.09.20.12.28.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:28:25 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 03/18] EDAC/synopsys: Extend memtypes supported by controller Date: Wed, 20 Sep 2023 22:26:48 +0300 Message-ID: <20230920192806.29960-4-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920192806.29960-1-fancer.lancer@gmail.com> References: <20230920192806.29960-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230920_122828_139401_3BA482C2 X-CRM114-Status: GOOD ( 18.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In accordance with [1] the DW uMCTL2 DDR controllers can support the next DDR protocols: LPDDR, (LP)DDR(2|3|4). Even if the controller is configured to support several of these memory chip types only one of these modes could be enabled at runtime [2]. Taking all of that into account update the snps_get_mtype() procedure so the DW uMCTL2 DDRC driver would be able to detect all the claimed to be supported memory types in accordance with the table defined in [2]. Note alas it's not possible do determine which MEMC DDR configs were enabled at the IP-core synthesize. Therefore there is no other choice but to initialize the EDAC MC mem-types capability field with all the types claimed to be supported by the IP-core. [1] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p.501 [2] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p.501 Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 41 ++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 10716f365c6f..e08e9f3c81cb 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -102,11 +102,14 @@ #define DDR_MSTR_BUSWIDTH_16 2 #define DDR_MSTR_BUSWIDTH_32 1 #define DDR_MSTR_BUSWIDTH_64 0 +#define DDR_MSTR_MEM_MASK GENMASK(5, 0) #define DDR_MSTR_MEM_LPDDR4 BIT(5) #define DDR_MSTR_MEM_DDR4 BIT(4) #define DDR_MSTR_MEM_LPDDR3 BIT(3) -#define DDR_MSTR_MEM_DDR2 BIT(2) +#define DDR_MSTR_MEM_LPDDR2 BIT(2) +#define DDR_MSTR_MEM_LPDDR BIT(1) #define DDR_MSTR_MEM_DDR3 BIT(0) +#define DDR_MSTR_MEM_DDR2 0 /* ECC CFG0 register definitions */ #define ECC_CFG0_MODE_MASK GENMASK(2, 0) @@ -535,21 +538,29 @@ static u32 snps_get_memsize(void) */ static enum mem_type snps_get_mtype(const void __iomem *base) { - enum mem_type mt; - u32 memtype; + u32 regval; - memtype = readl(base + DDR_MSTR_OFST); + regval = readl(base + DDR_MSTR_OFST); + regval = FIELD_GET(DDR_MSTR_MEM_MASK, regval); - if ((memtype & DDR_MSTR_MEM_DDR3) || (memtype & DDR_MSTR_MEM_LPDDR3)) - mt = MEM_DDR3; - else if (memtype & DDR_MSTR_MEM_DDR2) - mt = MEM_RDDR2; - else if ((memtype & DDR_MSTR_MEM_LPDDR4) || (memtype & DDR_MSTR_MEM_DDR4)) - mt = MEM_DDR4; - else - mt = MEM_EMPTY; + switch (regval) { + case DDR_MSTR_MEM_DDR2: + return MEM_DDR2; + case DDR_MSTR_MEM_DDR3: + return MEM_DDR3; + case DDR_MSTR_MEM_LPDDR: + return MEM_LPDDR; + case DDR_MSTR_MEM_LPDDR2: + return MEM_LPDDR2; + case DDR_MSTR_MEM_LPDDR3: + return MEM_LPDDR3; + case DDR_MSTR_MEM_DDR4: + return MEM_DDR4; + case DDR_MSTR_MEM_LPDDR4: + return MEM_LPDDR4; + } - return mt; + return MEM_RESERVED; } /** @@ -597,7 +608,9 @@ static void snps_mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) platform_set_drvdata(pdev, mci); /* Initialize controller capabilities and configuration */ - mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; + mci->mtype_cap = MEM_FLAG_LPDDR | MEM_FLAG_DDR2 | MEM_FLAG_LPDDR2 | + MEM_FLAG_DDR3 | MEM_FLAG_LPDDR3 | + MEM_FLAG_DDR4 | MEM_FLAG_LPDDR4; mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; mci->scrub_cap = SCRUB_FLAG_HW_SRC; mci->scrub_mode = SCRUB_NONE;