diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-common.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-common.yaml
new file mode 100644
index 000000000000..115fe5e8339a
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-common.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
+
+maintainers:
+  - Krzysztof Kozlowski <krzk@kernel.org>
+  - Manish Narani <manish.narani@xilinx.com>
+  - Michal Simek <michal.simek@xilinx.com>
+
+description:
+  Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
+  working with the memory devices supporting up to (LP)DDR4 protocol. It can
+  be equipped with SEC/DEC ECC feature if DRAM data bus width is either
+  16-bits or 32-bits or 64-bits wide.
+
+select: false
+
+properties:
+  interrupts:
+    description:
+      DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
+      ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,
+      Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the
+      signals merged before they reach the IRQ controller or have some of them
+      absent in case if the corresponding feature is unavailable/disabled.
+    minItems: 1
+    maxItems: 5
+
+  interrupt-names:
+    minItems: 1
+    maxItems: 5
+    oneOf:
+      - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ
+        items:
+          - const: ecc
+      - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs
+        items:
+          enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ]
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    description:
+      A standard set of the clock sources contains CSRs bus clock, AXI-ports
+      reference clock, DDRC core clock, Scrubber standalone clock
+      (synchronous to the DDRC clock).
+    minItems: 1
+    maxItems: 4
+
+  clock-names:
+    minItems: 1
+    maxItems: 4
+    items:
+      enum: [ pclk, aclk, core, sbr ]
+
+  resets:
+    description:
+      Each clock domain can have separate reset signal.
+    minItems: 1
+    maxItems: 4
+
+  reset-names:
+    minItems: 1
+    maxItems: 4
+    items:
+      enum: [ prst, arst, core, sbr ]
+
+additionalProperties: true
+
+...
diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
index 87ff9ee098f5..80b25d2fa974 100644
--- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
@@ -20,6 +20,11 @@ description: |
   controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
   bus width configurations.
 
+allOf:
+  - $ref: /schemas/memory-controllers/snps,dw-umctl2-common.yaml#
+
+# Please create a separate DT-schema for your DW uMCTL2 DDR controller
+# with more detailed properties definition.
 properties:
   compatible:
     oneOf:
@@ -31,62 +36,12 @@ properties:
       - description: Xilinx ZynqMP DDR controller v2.40a
         const: xlnx,zynqmp-ddrc-2.40a
 
-  interrupts:
-    description:
-      DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
-      ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,
-      Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the
-      signals merged before they reach the IRQ controller or have some of them
-      absent in case if the corresponding feature is unavailable/disabled.
-    minItems: 1
-    maxItems: 5
-
-  interrupt-names:
-    minItems: 1
-    maxItems: 5
-    oneOf:
-      - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ
-        items:
-          - const: ecc
-      - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs
-        items:
-          enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ]
-
-  reg:
-    maxItems: 1
-
-  clocks:
-    description:
-      A standard set of the clock sources contains CSRs bus clock, AXI-ports
-      reference clock, DDRC core clock, Scrubber standalone clock
-      (synchronous to the DDRC clock).
-    minItems: 1
-    maxItems: 4
-
-  clock-names:
-    minItems: 1
-    maxItems: 4
-    items:
-      enum: [ pclk, aclk, core, sbr ]
-
-  resets:
-    description:
-      Each clock domain can have separate reset signal.
-    minItems: 1
-    maxItems: 4
-
-  reset-names:
-    minItems: 1
-    maxItems: 4
-    items:
-      enum: [ prst, arst, core, sbr ]
-
 required:
   - compatible
   - reg
   - interrupts
 
-additionalProperties: false
+unevaluatedProperties: false
 
 examples:
   - |
