Message ID | 20230921100039.19897-2-r-gunasekaran@ti.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | AM68 SK: Add support for PCIe and USB | expand |
On Thu, 21 Sep 2023 15:30:37 +0530, Ravi Gunasekaran wrote: > From: Sinthu Raja <sinthu.raja@ti.com> > > Lanes 0 and 2 of the J721S2 SerDes WIZ are reserved for USB type-C > lane swap. Update the macro definition for it. > > Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> > Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> > --- > arch/arm64/boot/dts/ti/k3-serdes.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h index 29167f85c1f6..21b4886c47ba 100644 --- a/arch/arm64/boot/dts/ti/k3-serdes.h +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -111,7 +111,7 @@ #define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 #define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J721S2_SERDES0_LANE2_USB_SWAP 0x2 #define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 #define J721S2_SERDES0_LANE3_EDP_LANE3 0x0