From patchwork Thu Sep 28 07:06:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 13402133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3B9DCE7B07 for ; Thu, 28 Sep 2023 07:09:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Q3NQF0k2tUdjhItIStp3xhany9ywBBx08N9qMNEW/Sw=; b=jHLChfOQSloyEi Zl7qQhhLloYtksn7wHFfMp+0WhKhMZHZGLWin27Z3rZTIDaCBlUKDBRBB9VWLIOU+Uf6w7ndZrn9K 93gbULjmvk6VAgxrf8iQmRsAwZnhkxf1g+XlH51khg6QDggtsiy4wDb/NMDHseNIth4K3j9l8ymic KyVaM+o7wki6ourgjgC3TqkB05CG838aMr7CKphT0M+I/0Ch0J94p2zlz7XwgdwCPCLFTA3j9IUIR 4+LKFL8+aYd/XOg7sLAxb8MBXEGWqyhYazYpZL8vgRjkc+9daR3XRwRcngnyYaXJCI/E3DLsZugh5 4pJkOvmSmXEGVBrCqs1Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qll8o-002TJ7-14; Thu, 28 Sep 2023 07:08:54 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qll8I-002Sua-1Y for linux-arm-kernel@bombadil.infradead.org; Thu, 28 Sep 2023 07:08:22 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=VsO/shW7GdAWiIRATyL5QAf+hh5aGcox3ohTh+0Qx8Q=; b=RpKiyuSwXVAEBqfeWpE+TXIoI3 NuDmgEHBULKO2JuhCPHDx7mnFRDV9mNGsZ2O0saBs4z1+SYmin/CTrdv+V5AQUj5PCKLgLGsAuT1U 0N98yBlhrGL+ztBSkbrPIJBu+OQt3XBi0tTVO/wm3zIKguvXnXw/Na7hIjZ3Fdx6JwawQODb/XSK7 eVNaaG4N1SQrOa9v9VnIPIofDhXdPEZw0c9PD6qOyJ5u21bVzQztZN6RJ4nf2A8EpSj/Ej8YAnBKW 9o/oFaN4935F3KWrZuSjG4PcYw8CuF9BvG+Z6xR8jKgsg3dtI1e20pQ8YqGNYdlJjtpc+NXUqLlHO an58IOrg==; Received: from relay7-d.mail.gandi.net ([217.70.183.200]) by casper.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1qll8D-0013pW-0X for linux-arm-kernel@lists.infradead.org; Thu, 28 Sep 2023 07:08:19 +0000 Received: by mail.gandi.net (Postfix) with ESMTPA id C80C120002; Thu, 28 Sep 2023 07:08:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1695884893; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VsO/shW7GdAWiIRATyL5QAf+hh5aGcox3ohTh+0Qx8Q=; b=Qih0cEeJEeoaHZBRH0rdEwfUl8JqGAkp3ERik5aXr22HRHdlGcMJQ+ELiSEf8cGfEsBD7e xDHmoL9rltoFyWCy9DYxrZ4afZdz2flx140ha5LVlkDUWVUrYeX+aF5XRDRgMassnnj7Sd NvvBPDdaBsE+FHwW3qGj7w4umuzA12MtJH1V7xNYg/r3WuV8/+wkGEl+fz+zPP9W/ByBHr rHnq+8Osd+915niqJazC8EsepK1QTzxBBNSSsIl5/NLWAn+hLbhQfTnGpncECN3IZLQfKC vd5m8yvpEgTRG2Cux5Hi38dGbF7du6YbpAOu2H5jDrzO43uJfeB+pSG60co8SA== From: Herve Codina To: Herve Codina , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Qiang Zhao , Li Yang , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Christophe Leroy , Randy Dunlap Cc: netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, alsa-devel@alsa-project.org, Simon Horman , Christophe JAILLET , Thomas Petazzoni Subject: [PATCH v7 19/30] soc: fsl: cpm1: qmc: Introduce is_tsa_64rxtx flag Date: Thu, 28 Sep 2023 09:06:37 +0200 Message-ID: <20230928070652.330429-20-herve.codina@bootlin.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230928070652.330429-1-herve.codina@bootlin.com> References: <20230928070652.330429-1-herve.codina@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: herve.codina@bootlin.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230928_080817_107193_BAC7EF83 X-CRM114-Status: GOOD ( 14.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In order to support runtime timeslot route changes, some operations will be different according the routing table used (common Rx and Tx table or one table for Rx and one for Tx). The is_tsa_64rxtx flag is introduced to avoid extra computation to determine the table format each time we need it. It is set once at initialization. Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index eeceb81bf107..19acfcded9bc 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -216,6 +216,7 @@ struct qmc { u16 __iomem *int_curr; dma_addr_t int_dma_addr; size_t int_size; + bool is_tsa_64rxtx; struct list_head chan_head; struct qmc_chan *chans[64]; }; @@ -696,7 +697,7 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable) * Setup one common 64 entries table or two 32 entries (one for Tx * and one for Tx) according to assigned TS numbers. */ - if (info.nb_tx_ts > 32 || info.nb_rx_ts > 32) + if (chan->qmc->is_tsa_64rxtx) return qmc_chan_setup_tsa_64rxtx(chan, &info, enable); ret = qmc_chan_setup_tsa_32rx(chan, &info, enable); @@ -1053,6 +1054,7 @@ static int qmc_init_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info *in * Everything was previously checked, Tx and Rx related stuffs are * identical -> Used Rx related stuff to build the table */ + qmc->is_tsa_64rxtx = true; /* Invalidate all entries */ for (i = 0; i < 64; i++) @@ -1081,6 +1083,7 @@ static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_serial_info * Use a Tx 32 entries table and a Rx 32 entries table. * Everything was previously checked. */ + qmc->is_tsa_64rxtx = false; /* Invalidate all entries */ for (i = 0; i < 32; i++) {