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[v6,1/4] arm64: dts: lx2160a: describe the SerDes block #2

Message ID 20231001103259.11762-2-josua@solid-run.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: freescale: Add support for LX2162 SoM & Clearfog Board | expand

Commit Message

Josua Mayer Oct. 1, 2023, 10:32 a.m. UTC 
Add description for the LX2160A second SerDes block.
It is functionally identical to the first one already added in
commit 3cbe93a1f540 ("arch: arm64: dts: lx2160a: describe the SerDes
block #1").

The SerDes driver currently updates the registers of all 8 lanes by
default during probe. Because currently this driver only supports
configuration of network protocols, this can lead to problems with
certain configurations.
Set status property to "disabled" by default so that existing boards are
not impacted.

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
V4 -> V5: expand commit hash reference in commit message
V5 -> V6: status disabled by default

 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
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Patch

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index ea6a94b57aeb..f176ca2e244e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -626,6 +626,13 @@  serdes_1: phy@1ea0000 {
 			#phy-cells = <1>;
 		};
 
+		serdes_2: phy@1eb0000 {
+			compatible = "fsl,lynx-28g";
+			reg = <0x0 0x1eb0000 0x0 0x1e30>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
 		crypto: crypto@8000000 {
 			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 			fsl,sec-era = <10>;