From patchwork Sun Oct 1 18:14:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 13405456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA02FE78480 for ; Sun, 1 Oct 2023 18:15:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/kuZ7+FGjS0EbdGFOGqEWFKtfaCTbhlup5SIlqaMdhk=; b=up5Au7MFCcCHH0 FcEtQjC7c6JZMRvz2rBXxEmFs/yuXTR5dVoSLGPvnqqxQKjnqSi4OsPpcWVp5FHoK5ll+F5+ocY4L nJN+1rKlYNknJ/SvHurAbs1dsOJeinccYYGK/qPlqJeK3PXO9llik9fohVG1bLiyndSBaYTnNXOjL JHR6HWk1u3PvGX4YBa19n0YecSy/mr8xWT6/9yynWGEaxz1Z5MPJWk18eZLCajMcCUhH1o2Hqm9S8 XUrgVLp44ouyem4Jtd+M15iaITfKiP0pcF4g0u3JjurURlXlLWuiCzDaWhWeAQ2FwQCvZVr+7yMgR tH6dAfmaomys65q4/AzQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qn0xr-00BVPD-2r; Sun, 01 Oct 2023 18:14:47 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qn0xo-00BVMW-1H for linux-arm-kernel@lists.infradead.org; Sun, 01 Oct 2023 18:14:46 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 391IEeX5030314; Sun, 1 Oct 2023 13:14:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1696184080; bh=8WMbO9q3SxWWyKVwF6ExdlWmymE6m/bCtzduokZaMhM=; h=From:To:Subject:Date:In-Reply-To:References; b=Bn+Crmp5/m05FvoOo7MB/l7Fzj2e1ErNE/7UWPuToL3fJ8vZenaLUhChTXYiNZsQI TYBhR4LNZhxdBrsdKPcknfgXeduKjzpKuMMSWdaYel1I9rp8FehwltAsSgw6KB1fW0 hvz1fA+xFGMc1Bm3x8Lsw6H2TMcBDizZCP1c0/AY= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 391IEeDJ124550 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 1 Oct 2023 13:14:40 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sun, 1 Oct 2023 13:14:40 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sun, 1 Oct 2023 13:14:40 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 391IEHts063395; Sun, 1 Oct 2023 13:14:36 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Hari Nagalla , Udit Kumar Subject: [PATCH v5 5/9] arm64: dts : ti: k3-j721s2-som-p0: Add DDR carveout memory nodes for C71x DSPs Date: Sun, 1 Oct 2023 23:44:13 +0530 Message-ID: <20231001181417.743306-6-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231001181417.743306-1-a-nandan@ti.com> References: <20231001181417.743306-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231001_111444_513257_D98192C1 X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Two carveout reserved memory nodes each have been added for each of the C71x DSP for the TI J721S2 EVM boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The C71x DSP processor supports a MMU called CMMU, but is not currently supported and as such requires the exact memory used by the firmware to be set-aside. Signed-off-by: Hari Nagalla Signed-off-by: Apurva Nandan Reviewed-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 52 ++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 970340ff2c0a..dcad372620b1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -102,6 +102,30 @@ main_r5fss1_core1_memory_region: r5f-memory@a5100000 { no-map; }; + c71_0_dma_memory_region: c71-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: ipc-memories@a8000000 { reg = <0x00 0xa8000000 0x00 0x01c00000>; alignment = <0x1000>; @@ -272,6 +296,20 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { }; }; +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, @@ -307,3 +345,17 @@ &main_r5fss1_core1 { memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +};