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Mon, 02 Oct 2023 09:46:13 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:bb:b2b6:1831:5edd]) by smtp.gmail.com with ESMTPSA id n3-20020a170902d2c300b001c737950e4dsm8455904plc.2.2023.10.02.09.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 09:46:13 -0700 (PDT) From: Douglas Anderson To: Catalin Marinas , Will Deacon , Mark Rutland , Marc Zyngier Cc: Stephen Boyd , Valentin Schneider , Chen-Yu Tsai , Douglas Anderson , AngeloGioacchino Del Regno , D Scott Phillips , Josh Poimboeuf , Matthias Brugger , Misono Tomohiro , Peter Zijlstra , Sumit Garg , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 1/2] arm64: smp: Fix pseudo NMI issues w/ broken Mediatek FW Date: Mon, 2 Oct 2023 09:45:29 -0700 Message-ID: <20231002094526.1.Ie8f760213053e3d11592f892b30912dbac6b8b48@changeid> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231002_094616_980428_D992FBFB X-CRM114-Status: GOOD ( 17.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some mediatek devices have the property "mediatek,broken-save-restore-fw" in their GIC. This means that, although the hardware supports pseudo-NMI, the firmware has a bug that blocks enabling it. When we're in this state, system_uses_irq_prio_masking() will return true but we'll fail to actually enable the IRQ in the GIC. Let's make the code handle this. We'll detect that we failed to request an IPI as NMI and fallback to requesting it normally. Though we expect that either all of our requests will fail or all will succeed, it's just as cheap to keep a per-IPI bitmap and that keeps us robust. Fixes: 331a1b3a836c ("arm64: smp: Add arch support for backtrace using pseudo-NMI") Reported-by: Chen-Yu Tsai Closes: https://issuetracker.google.com/issues/197061987#comment68 Signed-off-by: Douglas Anderson Reported-by: Chen-Yu Tsai Signed-off-by: Mark Rutland Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson Reviewed-by: Marc Zyngier Tested-by: Chen-Yu Tsai --- arch/arm64/kernel/smp.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 814d9aa93b21..0a6002243a8c 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -87,6 +87,7 @@ enum ipi_msg_type { static int ipi_irq_base __ro_after_init; static int nr_ipi __ro_after_init = NR_IPI; static struct irq_desc *ipi_desc[MAX_IPI] __ro_after_init; +DECLARE_BITMAP(ipi_is_nmi, MAX_IPI); static void ipi_setup(int cpu); @@ -986,7 +987,7 @@ static void ipi_setup(int cpu) return; for (i = 0; i < nr_ipi; i++) { - if (ipi_should_be_nmi(i)) { + if (test_bit(i, ipi_is_nmi)) { prepare_percpu_nmi(ipi_irq_base + i); enable_percpu_nmi(ipi_irq_base + i, 0); } else { @@ -1004,7 +1005,7 @@ static void ipi_teardown(int cpu) return; for (i = 0; i < nr_ipi; i++) { - if (ipi_should_be_nmi(i)) { + if (test_bit(i, ipi_is_nmi)) { disable_percpu_nmi(ipi_irq_base + i); teardown_percpu_nmi(ipi_irq_base + i); } else { @@ -1022,17 +1023,21 @@ void __init set_smp_ipi_range(int ipi_base, int n) nr_ipi = min(n, MAX_IPI); for (i = 0; i < nr_ipi; i++) { - int err; + int err = -EINVAL; if (ipi_should_be_nmi(i)) { err = request_percpu_nmi(ipi_base + i, ipi_handler, "IPI", &cpu_number); - WARN(err, "Could not request IPI %d as NMI, err=%d\n", - i, err); - } else { + if (err) + pr_info_once("NMI unavailable; fallback to IRQ\n"); + else + set_bit(i, ipi_is_nmi); + } + + if (err) { err = request_percpu_irq(ipi_base + i, ipi_handler, "IPI", &cpu_number); - WARN(err, "Could not request IPI %d as IRQ, err=%d\n", + WARN(err, "Could not request IPI %d, err=%d\n", i, err); }