| Message ID | 20231003124544.858804-3-joey.gouly@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | HWCAP for FEAT_LSE128 | expand |
On Tue, Oct 03, 2023 at 01:45:44PM +0100, Joey Gouly wrote: > Add test of a 128-bit atomic instruction for FEAT_LSE128. > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > --- > tools/testing/selftests/arm64/abi/hwcap.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > asm volatile(".inst 0xb82003ff" : : : ); > } > > +static void lse128_sigill(void) > +{ ... > +} > + > static void crc32_sigill(void) > { Please keep things sorted alphabetically.
diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c index e3d262831d91..dd9a1cdfd294 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -46,6 +46,20 @@ static void atomics_sigill(void) asm volatile(".inst 0xb82003ff" : : : ); } +static void lse128_sigill(void) +{ + u64 __attribute__ ((aligned (16))) mem[2] = { 10, 20 }; + register u64 *memp asm ("x0") = mem; + register u64 val0 asm ("x1") = 5; + register u64 val1 asm ("x2") = 4; + + /* SWPP X1, X2, [X0] */ + asm volatile(".inst 0x19228001" + : "+r" (memp), "+r" (val0), "+r" (val1) + : + : "cc", "memory"); +} + static void crc32_sigill(void) { /* CRC32W W0, W0, W1 */ @@ -364,6 +378,13 @@ static const struct hwcap_data { .sigbus_fn = uscat_sigbus, .sigbus_reliable = true, }, + { + .name = "LSE128", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_LSE128, + .cpuinfo = "lse128", + .sigill_fn = lse128_sigill, + }, { .name = "MOPS", .at_hwcap = AT_HWCAP2,
Add test of a 128-bit atomic instruction for FEAT_LSE128. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> --- tools/testing/selftests/arm64/abi/hwcap.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)