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Fri, 6 Oct 2023 13:00:41 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20231006130041eusmtrp230bdbb5ee5dd38bb2b10626476a08e48~LhjOqCYQX0212502125eusmtrp2h; Fri, 6 Oct 2023 13:00:41 +0000 (GMT) X-AuditID: cbfec7f5-815ff7000002937e-9e-652004f9bb5f Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 5F.1E.10549.8F400256; Fri, 6 Oct 2023 14:00:41 +0100 (BST) Received: from AMDC4515.eu.corp.samsungelectronics.net (unknown [106.120.51.28]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20231006130040eusmtip21462b213c9f036b15634f5f0a6f3bf10~LhjOCzCT81292012920eusmtip2U; Fri, 6 Oct 2023 13:00:40 +0000 (GMT) From: Mateusz Majewski To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mateusz Majewski , Tomasz Figa , Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Marek Szyprowski Subject: [PATCH 2/4] pinctrl: samsung: use add_pin_ranges method to add pinctrl ranges Date: Fri, 6 Oct 2023 14:55:55 +0200 Message-ID: <20231006125557.212681-3-m.majewski2@samsung.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231006125557.212681-1-m.majewski2@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrMKsWRmVeSWpSXmKPExsWy7djP87o/WRRSDRY/lrV4MG8bm8Xe11vZ Lab8Wc5ksenxNVaLzfP/MFpc3jWHzWLG+X1MFhOPTWa2WHvkLrvF4TftrBardv1hdOD22Dnr LrvHnWt72Dw2L6n36NuyitHj8ya5ANYoLpuU1JzMstQifbsEroz2W/1MBScUKlY/f8zUwNgp 3cXIySEhYCIx7/4pti5GLg4hgRWMElfuT2KGcL4wSjxsOsUOUiUk8JlR4maPIkxH69W7TBBF yxkldn1oZIVwWpkkZmxcBNbBJmAg8eDNMnaQhIhAO6NEz61bjCAOs8A+JonJGy+yglQJC0RI bFqznAnEZhFQlZjUuI0ZxOYVsJWYPWkvM8Q+eYk9i76D1XAK2Ek0Pf/OAlEjKHFy5hMwmxmo pnnrbLDDJQSucEhMn/WSFaLZRWLiqYPsELawxKvjW6BsGYn/O+czQdj5EjM2vwcaxAFkV0jc PegFYVpLfDzDDGIyC2hKrN+lD1HsKLFw/nYmiAo+iRtvBSEO4JOYtG06M0SYV6KjTQiiWlXi +J5JUH9ISzxpuQ210kNi8uvpzBMYFWcheWUWkldmIexdwMi8ilE8tbQ4Nz212DgvtVyvODG3 uDQvXS85P3cTIzAdnf53/OsOxhWvPuodYmTiYDzEKMHBrCTCm94gkyrEm5JYWZValB9fVJqT WnyIUZqDRUmcVzVFPlVIID2xJDU7NbUgtQgmy8TBKdXA1N4957yWRs1LF3PLCLs/SzfV3pl2 42z9ywW233mZ+zIvl8U3lwWHGhve/XeKhWdd54mzb8uPKD6QWVC+QVEwx+vK4pMs6/p0X4g1 tnqXfXqzzLKgxEqcbaW14OVtGrInPb7/P9onyPAwPDf02TL12XHM9xLua/5paX/VZai7bAf3 N/0Dpz9UPIhe+vNiU0eQoVrMs/fdXJ+PTJ/OXFsjNc2gpuNNtOq6tbY7lZztzP2dxOfuTbs5 Vynq0NfuXSInJl/2Z2NrySs584ZxxuJ8zb+VimsupecfPbzwTznnrHtflSrlvVMZRV732ql/ r8qvT/T5U7iNOfXNZEatve0iorxXzJNrQ+XkH23kK7itxFKckWioxVxUnAgAqc8Gg7YDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprMIsWRmVeSWpSXmKPExsVy+t/xe7o/WRRSDbprLR7M28Zmsff1VnaL KX+WM1lsenyN1WLz/D+MFpd3zWGzmHF+H5PFxGOTmS3WHrnLbnH4TTurxapdfxgduD12zrrL 7nHn2h42j81L6j36tqxi9Pi8SS6ANUrPpii/tCRVISO/uMRWKdrQwkjP0NJCz8jEUs/Q2DzW yshUSd/OJiU1J7MstUjfLkEvo/1WP1PBCYWK1c8fMzUwdkp3MXJySAiYSLRevcvUxcjFISSw lFHi4M4V7BAJaYnDX6ZA2cISf651sUEUNTNJ3Py4hgUkwSZgIPHgzTKwIhGBbkaJbxO5QIqY BQ4wSSyZdZANJCEsECbx4do7MJtFQFViUuM2ZhCbV8BWYvakvcwQG+Ql9iz6zgRicwrYSTQ9 /w62QAio5tCOPUwQ9YISJ2c+AYszA9U3b53NPIFRYBaS1CwkqQWMTKsYRVJLi3PTc4sN9YoT c4tL89L1kvNzNzECY2fbsZ+bdzDOe/VR7xAjEwfjIUYJDmYlEd70BplUId6UxMqq1KL8+KLS nNTiQ4ymQHdPZJYSTc4HRm9eSbyhmYGpoYmZpYGppZmxkjivZ0FHopBAemJJanZqakFqEUwf EwenVAOTz7Wzck29V8vUNJsuF6+e/u75zHMLpptc2+656HZ469lQsURJ8SntFjL3+OXn3PX9 dHh7cE2H8O0rN1I3c7+an6v0f+uV1zERP1f0GXhO1z17dYGuUuBttcuzst3120NnB2/pdJvl tmyNoQLDVlclngM31FbUWVuGrjrtZuD3WmLvGt7s1dJ1qeLbOVLkf21RT5ep3L+qbKmm2MlO 2yui0bFb22/L702ZLegqf9tFgHGSqOmLK49/uvIwhUYtflloqSf/yKCql9HvznSTiK231Xdp LvvPauWdsdbro8cX25VPHj4vTZ/Wl7XLRPzHo9Ll/HIttrr51m68ceeOP7pXsTymZs+CqnK/ 865HF7QrsRRnJBpqMRcVJwIAenemsyYDAAA= X-CMS-MailID: 20231006130041eucas1p1fd945c734c0d35067107e7c699201bdb X-Msg-Generator: CA X-RootMTR: 20231006130041eucas1p1fd945c734c0d35067107e7c699201bdb X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20231006130041eucas1p1fd945c734c0d35067107e7c699201bdb References: <20231006125557.212681-1-m.majewski2@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231006_060043_418736_41E8C7F9 X-CRM114-Status: GOOD ( 16.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is preferable since we can read the base in the global GPIO numberspace from the chip instead of needing to select it ourselves. Past versions could not do this, since they needed to add all the ranges before enabling the pinctrl subsystem, which was done before registering the GPIO chip. However, right now we enable the pinctrl subsystem after registering the chip and so this became possible. Signed-off-by: Mateusz Majewski --- drivers/pinctrl/samsung/pinctrl-samsung.c | 31 +++++++++++++---------- drivers/pinctrl/samsung/pinctrl-samsung.h | 2 ++ 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index e496af72a587..511a3ac51f76 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -665,6 +665,21 @@ static int samsung_gpio_to_irq(struct gpio_chip *gc, unsigned offset) return (virq) ? : -ENXIO; } +static int samsung_add_pin_ranges(struct gpio_chip *gc) +{ + struct samsung_pin_bank *bank = gpiochip_get_data(gc); + + bank->grange.name = bank->name; + bank->grange.id = bank->id; + bank->grange.pin_base = bank->drvdata->pin_base + bank->pin_base; + bank->grange.base = gc->base; + bank->grange.npins = bank->nr_pins; + bank->grange.gc = &bank->gpio_chip; + pinctrl_add_gpio_range(bank->drvdata->pctl_dev, &bank->grange); + + return 0; +} + static struct samsung_pin_group *samsung_pinctrl_create_groups( struct device *dev, struct samsung_pinctrl_drv_data *drvdata, @@ -892,6 +907,7 @@ static int samsung_pinctrl_register(struct platform_device *pdev, /* for each pin, the name of the pin is pin-bank name + pin number */ for (bank = 0; bank < drvdata->nr_banks; bank++) { pin_bank = &drvdata->pin_banks[bank]; + pin_bank->id = bank; for (pin = 0; pin < pin_bank->nr_pins; pin++) { sprintf(pin_names, "%s-%d", pin_bank->name, pin); pdesc = pindesc + pin_bank->pin_base + pin; @@ -911,18 +927,6 @@ static int samsung_pinctrl_register(struct platform_device *pdev, return ret; } - for (bank = 0; bank < drvdata->nr_banks; ++bank) { - pin_bank = &drvdata->pin_banks[bank]; - pin_bank->grange.name = pin_bank->name; - pin_bank->grange.id = bank; - pin_bank->grange.pin_base = drvdata->pin_base - + pin_bank->pin_base; - pin_bank->grange.base = pin_bank->grange.pin_base; - pin_bank->grange.npins = pin_bank->nr_pins; - pin_bank->grange.gc = &pin_bank->gpio_chip; - pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange); - } - return 0; } @@ -947,6 +951,7 @@ static const struct gpio_chip samsung_gpiolib_chip = { .direction_input = samsung_gpio_direction_input, .direction_output = samsung_gpio_direction_output, .to_irq = samsung_gpio_to_irq, + .add_pin_ranges = samsung_add_pin_ranges, .owner = THIS_MODULE, }; @@ -963,7 +968,7 @@ static int samsung_gpiolib_register(struct platform_device *pdev, bank->gpio_chip = samsung_gpiolib_chip; gc = &bank->gpio_chip; - gc->base = bank->grange.base; + gc->base = drvdata->pin_base + bank->pin_base; gc->ngpio = bank->nr_pins; gc->parent = &pdev->dev; gc->fwnode = bank->fwnode; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 9af93e3d8d9f..173db20f70d3 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -148,6 +148,7 @@ struct samsung_pin_bank_data { * @eint_mask: bit mask of pins which support EINT function. * @eint_offset: SoC-specific EINT register or interrupt offset of bank. * @name: name to be prefixed for each pin in this pin bank. + * @id: id of the bank, propagated to the pin range. * @pin_base: starting pin number of the bank. * @soc_priv: per-bank private data for SoC-specific code. * @of_node: OF node of the bank. @@ -170,6 +171,7 @@ struct samsung_pin_bank { u32 eint_mask; u32 eint_offset; const char *name; + u32 id; u32 pin_base; void *soc_priv;