From patchwork Tue Oct 10 12:30:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 13415332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9832CD80C0 for ; Tue, 10 Oct 2023 12:34:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YoW8ngCcmVQcxg+4UpXPYl7EljBZOEWgrgHwvoY5pC8=; b=gMDg/KIeHukGRf 5M6xo4vsImOAGgu+y4jWQWDp00ykaMkBaw2mJqOfC4ZN67UMlNKAdNHCRPclFO4EGwh2Dr299rCdy Wc1bkZo90+m0k7y5j+zZYjG9yqzdJsQbIXEhucSazDn/k5isR/X0Ttwu9eFw2aCln9lyOLlpsfJIZ HB/ROs0K5mcZwULQ4OImQlf3nWkqdFdMKCWf0sVMuy9+ATnPUSMsorlh+UCZF/6seRV4N1hE6hjwR PLHTFNt3z7CMwhc16XGeP3mddKL6N3zu2AgZFv98GRB2ouZAQu9hWL+FoJKovtaaHqLmUbDitprdi zRYzwsAUv/3iF1SAB6nQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qqBvg-00DLga-38; Tue, 10 Oct 2023 12:33:40 +0000 Received: from szxga02-in.huawei.com ([45.249.212.188]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qqBvY-00DLcn-1W for linux-arm-kernel@lists.infradead.org; Tue, 10 Oct 2023 12:33:35 +0000 Received: from canpemm500009.china.huawei.com (unknown [172.30.72.56]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4S4Zwf0rHCzVlV2; Tue, 10 Oct 2023 20:29:54 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 10 Oct 2023 20:33:22 +0800 From: Yicong Yang To: , , , CC: , , , , , , , , Subject: [RFC PATCH 3/3] clocksource/drivers: Add HiSilicon system timer driver Date: Tue, 10 Oct 2023 20:30:33 +0800 Message-ID: <20231010123033.23258-4-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20231010123033.23258-1-yangyicong@huawei.com> References: <20231010123033.23258-1-yangyicong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231010_053332_838005_A7F48759 X-CRM114-Status: GOOD ( 21.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yicong Yang HiSilicon system timer is compatible with arm's generic timer specification but is enumerated through DSDT and can use SPI/LPI interrupt as timer interrupt. This patch adds the support for the timer. The driver probes the device IO memory and interrupt resources through DSDT and then reuse the codes of the arm_arch_timer for setup and register the clockevent device. Example DSDT node will be like: Device (TIM0) { Name (_HID, "HISI03F2") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (RBUF, ResourceTemplate () { QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, 0x0000000000000000, // Granularity 0x0000000401170000, // Range Minimum 0x0000000401170fff, // Range Maximum 0x0000000000000000, // Translation Offset 0x0000000000001000, // Length ,, , AddressRangeMemory, TypeStatic) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x000003C6, } }) Method (_CRS, 0, NotSerialized) { Return (RBUF) } } Signed-off-by: Yicong Yang --- drivers/clocksource/Kconfig | 10 ++++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-hisi-sys.c | 68 ++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) create mode 100644 drivers/clocksource/timer-hisi-sys.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 0ba0dc4ecf06..2e43cd6e2add 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -732,4 +732,14 @@ config GOLDFISH_TIMER help Support for the timer/counter of goldfish-rtc +config HISI_SYS_TIMER + tristate "HiSilicon system timer driver" + depends on ARM_ARCH_TIMER && ARM64 && ACPI + help + Support for HiSilicon system timer which used as a clockevent + device. + + This driver can also be built as a module. If so, the module + will be called timer_hisi_sys. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 368c3461dab8..39ababd0d4dd 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -89,3 +89,4 @@ obj-$(CONFIG_MSC313E_TIMER) += timer-msc313e.o obj-$(CONFIG_GOLDFISH_TIMER) += timer-goldfish.o obj-$(CONFIG_GXP_TIMER) += timer-gxp.o obj-$(CONFIG_CLKSRC_LOONGSON1_PWM) += timer-loongson1-pwm.o +obj-$(CONFIG_HISI_SYS_TIMER) += timer-hisi-sys.o diff --git a/drivers/clocksource/timer-hisi-sys.c b/drivers/clocksource/timer-hisi-sys.c new file mode 100644 index 000000000000..1ef39d97e83d --- /dev/null +++ b/drivers/clocksource/timer-hisi-sys.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for HiSilicon system timer driver. + * + * The device is fully compatible with ARM's Generic Timer specification. + * The device is enumerated through DSDT rather than GTDT and can use + * LPI interrupt besides SPI. + * + * Copyright (c) 2023 HiSilicon Technologies Co., Ltd. + * Author: Yicong Yang + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DRV_NAME "hisi_sys_timer" + +#define CNTFRQ 0x10 + +static const struct acpi_device_id hisi_sys_timer_acpi_ids[] = { + { "HISI03F2", 0 }, + { } +}; +MODULE_DEVICE_TABLE(acpi, hisi_sys_timer_acpi_ids); + +static int hisi_sys_timer_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + void __iomem *iobase; + int ret, irq; + u32 freq; + + iobase = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(iobase)) + return PTR_ERR(iobase); + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) + return dev_err_probe(dev, ret, "failed to get interrupt\n"); + + ret = arch_timer_mem_register(iobase, irq, false, DRV_NAME); + if (ret) + return dev_err_probe(dev, ret, "failed to register timer\n"); + + freq = readl_relaxed(iobase + CNTFRQ); + dev_info(dev, "%s works at %ldMHz\n", DRV_NAME, freq / HZ_PER_MHZ); + return 0; +} + +static struct platform_driver hisi_sys_timer_driver = { + .probe = hisi_sys_timer_probe, + .driver = { + .name = DRV_NAME, + .acpi_match_table = hisi_sys_timer_acpi_ids, + }, +}; +module_platform_driver(hisi_sys_timer_driver); + +MODULE_AUTHOR("Yicong Yang "); +MODULE_DESCRIPTION("HiSilicon system timer driver"); +MODULE_LICENSE("GPL");