| Message ID | 20231016111743.30331-2-miguel.luis@oracle.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization | expand |
> On 16 Oct 2023, at 11:17, Miguel Luis <miguel.luis@oracle.com> wrote: > > Some _EL12 encodings are missing. Add them. > > Reviewed-by: Eric Auger <eric.auger@redhat.com> > Signed-off-by: Miguel Luis <miguel.luis@oracle.com> > --- > arch/arm64/include/asm/sysreg.h | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 38296579a4fd..ba5db50effec 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -567,19 +567,30 @@ > #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) > > /* VHE encodings for architectural EL0/1 system registers */ > +#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0) I think there’s a nit here as BRBCR_EL12 could be placed before MIDR_EL1 so the file keeps its definitions in order. Miguel > #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) > +#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) > +#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3) > +#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) > +#define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1) > +#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6) > #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) > #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) > #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) > +#define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3) > #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) > #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) > #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) > #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) > #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) > #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) > +#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) > +#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0) > #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) > #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) > #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) > +#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) > +#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7) > #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) > #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) > #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) > -- > 2.39.2 >
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 38296579a4fd..ba5db50effec 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -567,19 +567,30 @@ #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) /* VHE encodings for architectural EL0/1 system registers */ +#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0) #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) +#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) +#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3) +#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) +#define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1) +#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6) #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) +#define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3) #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) +#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) +#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0) #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) +#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) +#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7) #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)