From patchwork Tue Oct 17 05:23:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 13424446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 195BECDB474 for ; Tue, 17 Oct 2023 05:24:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZZ6FijUsRZ0QWPynz8qIg/Ge/KZjbbQmLoweF90n1Hs=; b=3dQqOVAcqDK/ws C2PRKsl+5//KrhnVNCE2Fd8VqaKa5fqTRHiUE5EbOl4hvFIC+PIPNfIULyHSkrlxrQQh4Ll+Xzxev DguTZQTAe+6wyNN8DY0hx1LGJXaV80X/qIyOU7FrurCGMAKLVNJqsJ68Zh443wbtLz4gIiM9o6JBN 0/KYTi/nCE6B5KUvwhca7Dmad19gMsJInp4RJ5FL24gtHbBbcrI3LwUWGAQTcajH65xGZv/NHjRlo 9mxv82u1FXFgHg91l7SFb7pDfmHBBklOOxYBJ+plYdX268ageFBsIhgQ0RHgPHPAihaPBX7mZ215W jpv1E1xVKr+jZz2WFHJA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qscYS-00BHZQ-0n; Tue, 17 Oct 2023 05:23:44 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qscYO-00BHXY-0i for linux-arm-kernel@lists.infradead.org; Tue, 17 Oct 2023 05:23:42 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3C2961007; Mon, 16 Oct 2023 22:24:16 -0700 (PDT) Received: from u200865.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 724BB3F5A1; Mon, 16 Oct 2023 22:23:35 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, anshuman.khandual@arm.com, krisman@suse.de, broonie@kernel.org, james.morse@arm.com, ionela.voinescu@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v2 3/3] arm64: cpufeature: Change 32-bit EL0 to display enabled cores Date: Tue, 17 Oct 2023 00:23:22 -0500 Message-ID: <20231017052322.1211099-4-jeremy.linton@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231017052322.1211099-1-jeremy.linton@arm.com> References: <20231017052322.1211099-1-jeremy.linton@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231016_222340_307015_5AC76616 X-CRM114-Status: GOOD ( 10.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that we have the ability to display the list of cores with a feature when it is selectivly enabled, lets display the cores enabled for 32-bit use at EL0. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpufeature.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b7b67bac0e60..512cbe446b41 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1533,8 +1533,17 @@ static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) if (!has_cpuid_feature(entry, scope)) return allow_mismatched_32bit_el0; - if (scope == SCOPE_SYSTEM) - pr_info("detected: 32-bit EL0 Support\n"); + if (scope == SCOPE_SYSTEM) { + struct arm64_cpu_capabilities *has_32bit; + + has_32bit = (struct arm64_cpu_capabilities *)entry; + + has_32bit->cpus = system_32bit_el0_cpumask(); + if (has_32bit->cpus == cpu_possible_mask) + has_32bit->cpus = cpu_online_mask; + if (has_32bit->cpus == cpu_none_mask) + has_32bit->cpus = NULL; + } return true; } @@ -2307,9 +2316,11 @@ static const struct arm64_cpu_capabilities arm64_features[] = { ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, IMP) }, { + .desc = "32-bit EL0 Support", .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, .type = ARM64_CPUCAP_SYSTEM_FEATURE, .matches = has_32bit_el0, + .cpus = cpu_none_mask, ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) }, #ifdef CONFIG_KVM