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Tue, 17 Oct 2023 12:05:50 -0700 (PDT) Received: from ryzen9.fritz.box ([2a01:2a8:8f03:b001:fe65:a70:2777:ab31]) by smtp.gmail.com with ESMTPSA id bq14-20020a056402214e00b00537963f692esm1637990edb.0.2023.10.17.12.05.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 12:05:49 -0700 (PDT) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dunlap@infradead.org, e.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, ames.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v5 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support Date: Tue, 17 Oct 2023 21:05:43 +0200 Message-ID: <20231017190545.157282-4-bero@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231017190545.157282-1-bero@baylibre.com> References: <20231017190545.157282-1-bero@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231017_120556_069425_41092E46 X-CRM114-Status: GOOD ( 12.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Balsam CHIHI Add LVTS Driver support for MT8192. Co-developed-by: Nícolas F. R. A. Prado Signed-off-by: Nícolas F. R. A. Prado Signed-off-by: Balsam CHIHI Reviewed-by: Nícolas F. R. A. Prado [bero@baylibre.com: cosmetic changes, rebase] Signed-off-by: Bernhard Rosenkränzer Reviewed-by: Matthias Brugger Reviewed-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index c5a03bdf63e9d..487401424951d 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -89,6 +89,7 @@ #define LVTS_MSR_READ_TIMEOUT_US 400 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) +#define LVTS_HW_SHUTDOWN_MT8192 105000 #define LVTS_HW_SHUTDOWN_MT8195 105000 #define LVTS_MINIMUM_THRESHOLD 20000 @@ -1286,6 +1287,88 @@ static int lvts_resume(struct device *dev) return 0; } +static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { + { + .cal_offset = { 0x04, 0x08 }, + .lvts_sensor = { + { .dt_id = MT8192_MCU_BIG_CPU0 }, + { .dt_id = MT8192_MCU_BIG_CPU1 } + }, + .num_lvts_sensor = 2, + .offset = 0x0, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + .mode = LVTS_MSR_FILTERED_MODE, + }, + { + .cal_offset = { 0x0c, 0x10 }, + .lvts_sensor = { + { .dt_id = MT8192_MCU_BIG_CPU2 }, + { .dt_id = MT8192_MCU_BIG_CPU3 } + }, + .num_lvts_sensor = 2, + .offset = 0x100, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + .mode = LVTS_MSR_FILTERED_MODE, + }, + { + .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, + .lvts_sensor = { + { .dt_id = MT8192_MCU_LITTLE_CPU0 }, + { .dt_id = MT8192_MCU_LITTLE_CPU1 }, + { .dt_id = MT8192_MCU_LITTLE_CPU2 }, + { .dt_id = MT8192_MCU_LITTLE_CPU3 } + }, + .num_lvts_sensor = 4, + .offset = 0x200, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + .mode = LVTS_MSR_FILTERED_MODE, + } +}; + +static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { + { + .cal_offset = { 0x24, 0x28 }, + .lvts_sensor = { + { .dt_id = MT8192_AP_VPU0 }, + { .dt_id = MT8192_AP_VPU1 } + }, + .num_lvts_sensor = 2, + .offset = 0x0, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset = { 0x2c, 0x30 }, + .lvts_sensor = { + { .dt_id = MT8192_AP_GPU0 }, + { .dt_id = MT8192_AP_GPU1 } + }, + .num_lvts_sensor = 2, + .offset = 0x100, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset = { 0x34, 0x38 }, + .lvts_sensor = { + { .dt_id = MT8192_AP_INFRA }, + { .dt_id = MT8192_AP_CAM }, + }, + .num_lvts_sensor = 2, + .offset = 0x200, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset = { 0x3c, 0x40, 0x44 }, + .lvts_sensor = { + { .dt_id = MT8192_AP_MD0 }, + { .dt_id = MT8192_AP_MD1 }, + { .dt_id = MT8192_AP_MD2 } + }, + .num_lvts_sensor = 3, + .offset = 0x300, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + } +}; + static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { { .cal_offset = { 0x04, 0x07 }, @@ -1365,6 +1448,16 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { } }; +static const struct lvts_data mt8192_lvts_mcu_data = { + .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), +}; + +static const struct lvts_data mt8192_lvts_ap_data = { + .lvts_ctrl = mt8192_lvts_ap_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), +}; + static const struct lvts_data mt8195_lvts_mcu_data = { .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), @@ -1376,6 +1469,8 @@ static const struct lvts_data mt8195_lvts_ap_data = { }; static const struct of_device_id lvts_of_match[] = { + { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, + { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, {},